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integrated precision battery sensor for automotive aduc7036 rev. b information furni responsibility is a rights of third part license is granted trademarks and r box 9106, norwood, ma 02062-9106, u.s.a. www.analog.com 2010 analog devices, inc. all rights reserved. shed by analog devices is believed to be accurate and reliable. however, no ssumed by analog devices for its use, nor for any infringements of patents or other ies that may result from its use. specifications subject to change without notice. no by implication or otherwise under any patent or patent rights of analog devices. egistered trademarks are the property of their respective owners. one technology way, p.o. tel: 781.329.4700 fax: 781.461.3113 ?2008C features high precision adcs dual channel, simultaneous sampling, 16-bit, - adcs programmable adc throughput from 1 hz to 8 khz on-chip 5 ppm/c voltage reference current channel fully differential, buffered input programmable gain from 1 to 512 adc input range: ?200 mv to +300 mv digital comparators with current accumulator feature voltage channel buffered, on-chip attenuator for 12 v battery inputs temperature channel external and on-chip temperature sensor options microcontroller arm7tdmi core, 16-/32-bit risc architecture 20.48 mhz pll with programmable divider pll input source on-chip precision oscillator on-chip low power oscillator external (32.768 khz) watch crystal jtag port supports code download and debug memory 96 kb flash/ee memory, 6 kb sram 10,000-cycle flash/ee endurance, 20-year flash/ee retention in-circuit download via jtag and lin on-chip peripherals saej2602/lin 2.0-compatible (slave) support via uart with hardware synchronization flexible wake-up i/o pin, master/slave spi serial i/o 9-pin gpio port, 3 general-purpose timers wake-up and watchdog timers power supply monitor and on-chip power-on reset power operates directly from 12 v battery supply current consumption normal mode 10 ma at 10 mhz low power monitor mode package and temperature range 48-lead, 7 mm 7 mm lfcsp fully specified for ?40c to +115c operation applications battery sensing/management for automotive systems functional block diagram ntrst tms tdo tck tdi precision analog acquisition buf result accumulator digital comparator temperature sensor vref vtemp vbat iin? iin+ precision reference pga 2.6v ldo psm por arm7tdmi mcu 20mhz 3 timers wdt wu timer memory 98kb flash 6kb ram aduc7036 precision osc low power osc on-chip pll gpio port uart port spi port lin mux buf 16-bit - adc vdd 16-bit - adc reset gnd_sw reg_avdd reg_dvdd agnd dgnd vss io_vss gpio_2/miso gpio_3/mosi gpio_1/sclk gpio_4/eclk g pio_5/irq1/rxd gpio_6/txd gpio_7/irq4 gpio_8/irq5 xtal1 xtal2 wu sti lin/bsd 0 7474-001 gpio_0/irq0/ss figure 1.
aduc7036 rev. b | page 2 of 132 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 3 ? specifications ..................................................................................... 4 ? electrical specifications ............................................................... 4 ? timing specifications ................................................................ 10 ? absolute maximum ratings .......................................................... 15 ? esd caution ................................................................................ 15 ? pin configuration and function descriptions ........................... 16 ? typical performance characteristics ........................................... 18 ? terminology .................................................................................... 19 ? theory of operation ...................................................................... 20 ? overview of the arm7tdmi core ......................................... 20 ? memory organization ............................................................... 22 ? reset ............................................................................................. 24 ? flash/ee memory ........................................................................... 25 ? programming flash/ee memory in-circuit .......................... 25 ? flash/ee control interface ........................................................ 25 ? flash/ee memory security ....................................................... 29 ? flash/ee memory reliability .................................................... 31 ? code execution time from sram and flash/ee ..................... 31 ? on-chip kernel .......................................................................... 32 ? memory mapped registers ....................................................... 34 ? complete mmr listing ............................................................. 35 ? 16-bit, - analog-to-digital converters .................................. 41 ? current channel adc (i-adc) .............................................. 41 ? adc ground switch .................................................................. 44 ? adc noise performance tables ............................................... 44 ? adc mmr interface ................................................................. 45 ? adc power modes of operation ............................................. 54 ? adc comparator and accumulator ....................................... 55 ? adc sinc3 digital filter response .......................................... 55 ? adc calibration ........................................................................ 58 ? adc diagnostics ........................................................................ 59 ? power supply support circuits ..................................................... 60 ? system clocks ................................................................................. 61 ? system clock registers .............................................................. 62 ? low power clock calibration ................................................... 65 ? processor reference peripherals ................................................... 67 ? interrupt system ......................................................................... 67 ? timers .............................................................................................. 70 ? synchronization across asynchronous clock domains ...... 70 ? programming the timers .......................................................... 71 ? timer0lifetime timer ........................................................... 73 ? timer1general-purpose timer ........................................... 75 ? timer2wake-up timer ......................................................... 77 ? timer3watchdog timer ........................................................ 79 ? timer4sti timer ................................................................... 81 ? general-purpose i/o ..................................................................... 83 ? high voltage peripheral control interface ................................. 94 ? wake-up (wu) pin ................................................................. 101 ? handling interrupts from the high voltage peripheral control interface ...................................................................... 102 ? low voltage flag (lvf) ........................................................... 102 ? high voltage diagnostics ........................................................ 102 ? uart serial interface .................................................................. 103 ? baud rate generation .............................................................. 103 ? uart register definitions ..................................................... 104 ? serial peripheral interface ........................................................... 109 ? miso pin ................................................................................... 109 ? mosi pin ................................................................................... 109 ? sclk pin ................................................................................... 109 ? ss pin ......................................................................................... 109 ? spi register definitions .......................................................... 109 ? serial test interface ...................................................................... 112 ? lin (local interconnect network) interface............................ 115 ? lin mmr description ............................................................ 115 ? lin hardware interface .......................................................... 119 ? bit serial device (bsd) interface ............................................... 123 ? bsd communication hardware interface ............................ 123 ? bsd related mmrs ................................................................. 124 ? bsd communication frame .................................................. 125 ? bsd data reception................................................................. 126 ? bsd data transmission ........................................................... 126 ? wake-up from bsd interface ................................................. 126 ? part identification ......................................................................... 127 ? schematic ....................................................................................... 130 ? outline dimensions ..................................................................... 131 ? ordering guide ........................................................................ 131 ?
aduc7036 rev. b | page 3 of 132 revision history 5 /10rev. a to rev. b changes to table 6 .......................................................................... 15 changes to timers section ............................................................ 70 7/09rev. 0 to rev. a changes to features section ............................................................ 1 changes to figure 1 ........................................................................... 1 changes to table 1 ....................................................................4, 8, 9 changes to table 3 .......................................................................... 11 changes to table 4 .......................................................................... 12 changes to table 5 .......................................................................... 13 changes to figure 8, figure 9, and figure 10 .............................. 18 changes to theory of operation section .................................... 20 changes to flash/ee memory reliability section ...................... 31 changes to table 46 ........................................................................ 64 changes to normal interrupt (irq) request section ............... 68 changes to timer0liftime timer section ............................... 71 changes to timer1 section ............................................................ 73 changes to timer2wake-up timer section ........................... 75 changes to timer3 interface section ........................................... 77 changes to timer4sti timer section ..................................... 79 changes to bsd communication frame section ..................... 123 changes to table 97 ...................................................................... 125 changes to figure 57 .................................................................... 128 changes to ordering guide ......................................................... 129 10/08revision 0: initial version
aduc7036 rev. b | page 4 of 132 specifications electrical specifications vdd = 3.5 v to 18 v, vref = 1.2 v internal reference, f core = 20.48 mhz (unless otherwise noted) driven from external 32.768 khz watch crystal or on-chip precision oscillator. all specifications t a = ?40c to +115c, unless otherwise noted. table 1. parameter test conditions/comments min typ max unit adc specifications conversion rate 1 chop off, adc normal operating mode 4 8000 hz chop on, adc normal operating mode 4 2600 hz chop on, adc low power mode 1 650 hz current channel no missing codes 1 valid for all adc update rates and adc modes 16 bits integral nonlinearity 1 , 2 10 60 ppm of fsr offset error 2 , 3 , 4 , 5 chop off, 1 lsb = (36.6/gain) v ?10 3 +10 lsb offset error 1 , 3 , 6 chop on ?2 0.5 +2 v offset error 1 , 3 chop on, low power or low power plus mode, mcu powered down 100 ?50 ?300 nv offset error 1 , 3 chop on, normal mode +0.5 ?1.25 ?3 v offset error drift 6 chop off, valid for adc gains of 4 to 64, normal mode 0.03 lsb/c offset error drift 6 chop off, valid for adc gains of 128 to 512, normal mode 30 nv/c offset error drift 6 chop on 10 nv/c total gain error 1 , 3 , 7 , 8 , 9 , 10 normal mode ?0.5 0.1 +0.5 % total gain error 1 , 3 , 7 , 9 low power mode, using adcref mmr ?4 0.2 +4 % total gain error 1 , 3 , 7 , 9 , 11 low power plus mode, using precision vref ?1 0.2 +1 % gain drift 3 ppm/c pga gain mismatch error 0.1 % output noise 1 , 12 4 hz update rate, gain = 512, adcflt = 0xbf1d 60 90 nv rms 4 hz update rate, gain = 512, adcflt = 0x3f1d 75 115 nv rms 10 hz update rate, gain = 512, adcflt = 0x961f 100 150 nv rms 10 hz update rate, gain = 512, adcflt = 0x161f 120 180 nv rms 1 khz update rate, gain 64, adcf lt = 0x8101 0.8 1.2 v rms 1 khz update rate, gain 64, adcflt = 0x0101 1 1.5 v rms 1 khz update rate, gain = 512, ad cflt = 0x0007 0.6 0.9 v rms 1 khz update rate, gain = 32, ad cflt = 0x0007 0.8 1.2 v rms 1 khz update rate, gain = 8, adcf lt = 0x8101 2.1 4.1 v rms 1 khz update rate, gain = 8, adcf lt = 0x0007 1.6 2.4 v rms 1 khz update rate, gain = 8, adcf lt = 0x0101 2.6 3.9 v rms 1 khz update rate, gain = 4, ad cflt = 0x0007 2.0 2.8 v rms 8 khz update rate, gain = 32, ad cflt = 0x0000 2.5 3.5 v rms 8 khz update rate, gain = 4, adcflt = 0x0000 14 21 v rms adc low power mode, f adc = 10 hz, gain = 128 1.25 1.9 v rms adc low power mode, f adc = 1 hz, gain = 128 0.35 0.5 v rms adc low power plus mode, f adc = 1 hz, gain = 512 0.1 0.15 v rms adc low power plus mode, f adc = 250 hz, gain = 512 0.6 0.9 v rms
aduc7036 rev. b | page 5 of 132 parameter test conditions/comments min typ max unit voltage channel 13 no missing codes 1 valid at all adc update rates 16 bits integral nonlinearity 1 10 60 ppm of fsr offset error 3 , 5 chop off, 1 lsb = 439.5 v ?10 1 +10 lsb offset error 1 , 3 chop on 0.3 1 lsb offset error drift chop off 0.03 lsb/c total gain error 1 , 3 , 7 , 10 , 14 includes resistor mismatch ?0.25 0.06 +0.25 % total gain error 1 , 3 , 7 , 10 , 14 temperature range = ?25c to +65c ?0.15 0.03 +0.15 % gain drift includes resistor mismatch drift 3 ppm/c output noise 1 , 12 , 15 4 hz update rate, adcflt = 0xbf1d 60 90 v rms 10 hz update rate, adcflt = 0x961f 60 90 v rms 1 khz update rate, adcflt = 0x0007 180 270 v rms 1 khz update rate, adcflt = 0x8101 240 307 v rms 1 khz update rate, adcflt = 0x0101 270 405 v rms 8 khz update rate, adcflt = 0x0000 1600 2400 v rms temperature channel no missing codes 1 valid at all adc update rates 16 bits integral nonlinearity 1 10 60 ppm of fsr offset error 3 , 4 , 5 , 16 chop off, 1 lsb = 19.84 v in unipolar mode ?10 3 +10 lsb offset error 1 , 3 chop on ?5 +1 +5 lsb offset error drift chop off 0.03 lsb/c total gain error 1 , 3 , 14 using reg_avdd as the reference ?0.2 0.06 +0.2 % gain drift 3 ppm/c output noise 1 1 khz update rate 7.5 11.25 v rms adc specifications analog input internal vref = 1.2 v current channel absolute input voltage range applies to both iin+ and iin? ?200 +300 mv input voltage range 17 , 18 gain = 1 19 1.2 v gain = 2 19 600 mv gain = 4 19 300 mv gain = 8 150 mv gain = 16 75 mv gain = 32 37.5 mv gain = 64 18.75 mv gain = 128 9.375 mv gain = 256 4.68 mv gain = 512 2.3 mv input leakage current 1 ?3 +3 na input offset current 1 , 20 0.5 1.5 na voltage channel absolute input voltage range 4 18 v input voltage range 0 to 28.8 v vbat input current vbat = 18 v 3 5.5 8 a temperature channel vref = (reg_avdd and gnd_sw)/2 absolute input voltage range 100 1300 mv input voltage range 0 to vref v vtemp input current 1 2.5 100 na
aduc7036 rev. b | page 6 of 132 parameter test conditions/comments min typ max unit voltage reference adc precision reference internal vref 1.2 v power-up time 1 0.5 ms initial accuracy 1 measured at t a = 25c ?0.15 +0.15 % temperature coefficient 1 , 21 ?20 5 +20 ppm/c reference long-term stability 22 100 ppm/1000 hr external reference input range 23 0.1 1.3 v vref divide-by-2 initial error 1 0.1 0.3 % adc low power reference internal vref 1.2 v initial accuracy measured at t a = 25c ?5 +5 % initial accuracy 1 using adcref, measured at t a = 25c 0.1 % temperature coefficient 1 , 21 ?300 150 +300 ppm/c adc diagnostics vref/136 1 at any gain settings 8.5 9.4 mv voltage attenuator current source 1 differential voltage increa se on the attenuator when the current source is on, temperature range = ?40c to +85c 3.1 3.8 v resistive attenuator divider ratio 24 resistor mismatch drift 3 ppm/c adc ground switch resistance direct path to ground 10 resistance 1 20 k resistor selected 10 20 30 k input current allowed contunious current through the switch with direct path to ground 6 ma temperature sensor 24 after user calibration accuracy mcu in power-down or standby mode 3 c mcu in power-down or standby mode, temperature range = ?25c to +65c 2 c power-on reset (por) por trip level refers to voltage at vdd pin 2.85 3 3.15 v por hysteresis 300 mv reset timeout from por 20 ms low voltage flag (lvf) lvf level refers to voltage at vdd pin 1.9 2.1 2.3 v power supply monitor (psm) psm trip level refers to voltage at vdd pin 6 v watchdog timer (wdt) timeout period 1 32.768 khz clock, 256 prescale 0.008 512 sec timeout step size 7.8 ms flash/ee memory 1 endurance 25 10,000 cycles data retention 26 20 years digital inputs all digital inputs except ntrst input leakage current input high = reg_dvdd 1 10 a input pull-up current input low = 0 v ?80 ?20 ?10 a input capacitance 10 pf input leakage current ntrst only: input low = 0 v 1 10 a input pull-down current ntrst only: input high = reg_dvdd 30 55 100 a
aduc7036 rev. b | page 7 of 132 parameter test conditions/comments min typ max unit logic inputs 1 all logic inputs v inl , input low voltage 0.4 v v inh , input high voltage 2 v crystal oscillator 1 logic inputs, xtal1 only v inl , input low voltage 0.8 v v inh , input high voltage 1.7 v xtal1 capacitance 12 pf xtal2 capacitance 12 pf on-chip oscillators low power oscillator 131.072 khz accuracy 27 includes drift data from 1000 hour life test ?3 +3 % precision oscillator 131.072 khz accuracy includes drift data from 1000 hour life test ?1 +1 % mcu clock rate eight programmable core clock selections within this range (binary divisions 1, 2, 4, 8,64, 128) 0.16 10.24 20.48 mhz mcu start-up time at power-on includes kernel po wer-on execution time 25 ms after reset event includes kernel power-on execution time 5 ms from mcu power-down oscillator running wake up from interrupt 2 ms wake up from lin 2 ms crystal powered down wake up from interrupt 500 ms internal pll lock time 1 ms lin input/output general baud rate 1000 20,000 bits/sec vdd supply voltage range at which the lin interface is functional 7 18 v input capacitance 5.5 pf input leakage current input (low) = io_vss ?800 ?400 a lin comparator response time 1 using 22 resistor 38 90 s i lin_dom_max current limit for driver when lin bus is in dominant state, vbat = vbat (max) 40 200 ma i lin_pas_rec driver off, 7 v < v lin < 18 v, vdd = v lin ? 0.7 v ?20 +20 a i lin 1 vbat disconnected, vdd = 0 v, 0 < v lin < 18 v 10 a i lin_pas_dom 1 input leakage v lin = 0 v ?1 ma i lin_no_gnd 28 control unit disconnected from ground, gnd = vdd, 0 v < v lin < 18 v, vbat = 12 v ?1 +1 ma v lin_dom 1 lin receiver dominant state, vdd > 7 v 0.4 vdd v v lin_rec 1 lin receiver recessive state, vdd > 7 v 0.6 vdd v v lin_cnt 1 lin receiver center voltage, vdd > 7 v 0.475 vdd 0.5 vdd 0.525 vdd v v hys 1 lin receiver hysteresis voltage 0.175 vdd v v lin_dom_drv_losup 1 lin dominant output voltage, vdd = 7 v r load = 500 1.2 v r load = 1000 0.6 v v lin_dom_drv_hisup 1 lin dominant output voltage, vdd = 18 v r load = 500 2 v r load = 1000 0.8 v v lin_recessive lin recessive output voltage 0.8 vdd v vbat shift 28 0 0.1 vdd v gnd shift 28 0 0.1 vdd v
aduc7036 rev. b | page 8 of 132 parameter test conditions/comments min typ max unit r slave slave termination resistance 20 30 47 k v serial diode 28 voltage drop at the serial diode, d ser_int 0.4 0.7 1 v symmetry of transmit propagation delay 1 vdd (min) = 7 v ?2 +2 s receive propagation delay 1 vdd (min) = 7 v 6 s symmetry of receive propagation delay 1 vdd (min) = 7 v ?2 +2 s lin version 1.3 specification bus load conditions (c bus ||r bus ):1 nf ||1 k; 6.8 nf || 660 ; 10 nf || 500 1 slew rate dominant and recessive edges, vbat = 18 v 1 2 3 v/s dt dv dt dv 1 slew rate dominant and recessive edges, vbat = 7 v 0.5 3 v/s t sym 1 symmetry of rising and falling edge, vbat = 18 v ?5 +5 s symmetry of rising and falling edge, vbat = 7 v ?4 +4 s lin version 2.0 specification bus load conditions (c bus ||r bus ): 1 nf||1 k; 6.8 nf||660 ; 10 nf||500 d1 duty cycle 1, th rec (max) = 0.744 vbat, th dom (max) = 0.581 vbat, v sup = 7 v18 v; t bit = 50 s, d1 = t bus_rec (min) /(2 t bit ) 0.396 d2 duty cycle 2, th rec (min) = 0.284 vbat, th dom (min) = 0.422 vbat, v sup = 7 v18 v; t bit = 50 s, d2 = t bus_rec (max) /(2 t bit ) 0.581 bsd input/output 29 baud rate 1164 1200 1236 bits/sec input leakage current input high = vdd, or input low = io_vss ?50 +50 a v ol , output low voltage 1.2 v v oh , output high voltage 0.8 vdd v i o(sc) short-circuit output current v bsd = vdd = 12 v 50 80 120 ma v inl , input low voltage 1.8 v v inh , input high voltage 0.7 vdd v wake up r load = 300 , c bus = 91 nf, r limit = 39 vdd 1 supply voltage range at which the wu pin is functional 7 18 v input leakage current input high = vdd 0.4 2.1 ma input low = io_vss ?50 +50 a v oh 30 output high level 5 v v ol 30 output low level 2 v v ih input high level 4.6 v v il input low level 1.2 v monoflop timeout timeout period 0.6 1.3 2 sec i o(sc) short-circuit output current 100 140 ma serial test interface r load = 500 , c bus = 2.4 nf, r limit = 39 baud rate 40 kbps input leakage current input high = vdd or input low = io_vss ?50 +70 a vdd supply voltage range for which sti is functional 7 18 v v oh output high level 0.6 vdd v v ol output low level 0.4 vdd v v ih input high level 0.6 vdd v v il input low level 0.4 vdd v
aduc7036 rev. b | page 9 of 132 parameter test conditions/comments min typ max unit package thermal specifications thermal shutdown 1 , 31 140 150 160 c thermal impedance ( ja ) 32 48-lead lfcsp, stacked die 45 c/w power requirements power supply voltages vdd (battery supply) 3.5 18 v reg_dvdd, reg_avdd 33 2.5 2.6 2.7 v power consumption i dd (mcu normal mode) 34 mcu clock rate = 10.24 mhz, adc off 10 20 ma mcu clock rate = 20.48 mhz, adc off (valid for aduc7036ccpz only) 20 30 ma i dd (mcu powered down) 1 adc low power mode, measured over the range of t a = ?10c to +40c, continuous adc conversion 300 400 a adc low power mode, measured over the range of t a = ?40c to +85c, continuous adc conversion 300 500 a adc low power plus mode, measured over the range of t a = ?10c to +40c, continuous adc conversion 520 700 a average current, measured with wake-up and watchdog timer clocked from the low power oscillator, t a = ?40c to +85c 120 300 a i dd (mcu powered down) average current, measured with wake-up and watchdog timer clocked from low power oscillator over a range of t a = ?10c to +40c 120 175 a i dd (current adc) 1.7 ma i dd (voltage/temperature adc) 0.5 ma i dd (precision oscillator) 400 a 1 these numbers are not production tested but are guaranteed by design and/or characterization data at production release. 2 valid for current adc gain setting of pga = 4 to 64. 3 these numbers include temperature drift. 4 tested at gain range = 4; self-offset calibration removes this error. 5 measured with an internal short after an initial offset calibration. 6 measured with an internal short. 7 these numbers include internal reference temperature drift. 8 factory-calibrated at gain = 1. 9 system calibration at a specific gain range (and temperat ure) removes the error at this g ain range (and temperature). 10 includes an initial system calibration. 11 using adc normal mode voltage reference. 12 typical noise in low power mode s is measured with chop enabled. 13 voltage channel specifications includ e resistive attenuator input stage. 14 system calibration removes this er ror at the specified temperature. 15 rms noise is referred to voltage attenuator input (for example, at f adc = 1 khz, typical rms noise at the adc input is 7.5 v) and scaled by the attenuator (divide-by-24) to yield these input referred noise specifications/values. 16 valid after an initial self-calibration. 17 in adc low power mode, the input range is fixed at 9.375 mv. in adc low power plus mode, the input range is fixed at 2.34375 mv. 18 it is possible to extend the adc input range by up to 10% by modifying the factory set value of the gain calibration register or using system calibration. this approach can also be used to reduce the adc input range (lsb size). 19 limited by minimum/maximum abso lute input voltage range. 20 valid for a differential input less than 10 mv. 21 measured using box method. 22 the long-term stability specification is noncumulative. the drift in subsequent 1000 hour periods is sign ificantly lower than in the first 1000 hour period. 23 references of up to reg_avdd can be accommodated by enabling an internal divide-by-2. 24 die temperature. 25 endurance is qualified to 10,000 cycles as per jedec std. 22 method a117 and measured at ?40c, +25c, and +125c. typical end urance at 25c is 170,000 cycles. 26 retention lifetime equivalent at junction temperature (t j ) of 85c as per jedec std. 22 me thod a117. retention lifetime de rates with junction temperature. 27 low power oscillator can be calibrated ag ainst either the precision oscillator or the external 32.768 khz crystal in user code . 28 these numbers are not production tested, but are supported by lin compliance testing. 29 bsd electrical specifications, except high and low voltage levels, are per lin 2.0 with pull-up resistor disabled and c l = 10 nf maximum. 30 specified after r limit of 39 . 31 the mcu core is not shut down but interrup ted, and high voltage i/o pins are disabled in response to a thermal shutdown event. 32 thermal impedance can be used to calculate the thermal gradient from ambient to die temperature. 33 internal regulated suppl y available at reg_dvdd (i source = 5 ma), and reg_avdd (i source = 1 ma). 34 the specification listed is typical; additional supply current co nsumed during flash/ee memory program and erase cycles is 7 m a and 5 ma, respectively.
aduc7036 rev. b | page 10 of 132 timing specifications spi timing specifications table 2. spi master mode timingphase mode = 1 parameter description min typ max unit t sl sclk low pulse width 1 (spidiv + 1) t hclk ns t sh sclk high pulse width 1 (spidiv + 1) t hclk ns t dav data output valid after sclk edge 2 (2 t uclk ) + (2 t hclk ) ns t dsu data input setup time before sclk edge 0 ns t dhd data input hold time after sclk edge 2 3 t uclk ns t df data output fall time 3.5 ns t dr data output rise time 3.5 ns t sr sclk rise time 3.5 ns t sf sclk fall time 3.5 ns 1 t hclk depends on the clock divider (cd) bits in the powcon mmr. t hclk = t uclk /2 cd . 2 t uclk = 48.8 ns. it corresponds to the 20.48 mhz internal clock from the pll before the clock divider. sclk (polarity = 0) sclk (polarity = 1) mosi miso msb in bits[6:1] lsb in lsb bits[6:1] msb t sh t sl t sr t sf t dav t df t dr t dsu t dhd 07474-002 figure 2. spi master mode timing?phase mode = 1
aduc7036 rev. b | page 11 of 132 table 3. spi master modephase mode = 0 parameter description min typ max unit t sl sclk low pulse width 1 (spidiv + 1) t hclk ns t sh sclk high pulse width 1 (spidiv + 1) t hclk ns t dav data output valid after sclk edge 2 (2 t uclk ) + (2 t hclk ) ns t dosu data output setup before sclk edge 0.5 t sl ns t dsu data input setup time before sclk edge 0 ns t dhd data input hold time after sclk edge 2 3 t uclk ns t df data output fall time 3.5 ns t dr data output rise time 3.5 ns t sr sclk rise time 3.5 ns t sf sclk fall time 3.5 ns 1 t hclk depends on the clock divider (cd) bits in the powcon mmr. t hclk = t uclk /2 cd . 2 t uclk = 48.8 ns. it corresponds to the 20.48 mhz internal clock from the pll before the clock divider. sclk (polarity = 0) sclk (polarity = 1) t sh t sl t sr t sf miso msb in bits[6:1] lsb in t dsu t dhd t dav t df t dr t dosu mosi lsb bits[6:1] msb 0 7474-003 figure 3. spi master mode timingphase mode = 0
aduc7036 rev. b | page 12 of 132 table 4. spi slave mode timingphase mode = 1 parameter description min typ max unit t ss ss to sclk edge 0.5 t sl ns t sl sclk low pulse width 1 (spidiv + 1) t hclk ns t sh sclk high pulse width 1 (spidiv + 1) t hclk ns t dav data output valid after sclk edge 2 (3 t uclk ) + (2 t hclk ) ns t dsu data input setup time before sclk edge 0 ns t dhd data input hold time after sclk edge 2 4 t uclk ns t df data output fall time 3.5 ns t dr data output rise time 3.5 ns t sr sclk rise time 3.5 ns t sf sclk fall time 3.5 ns t sfs ss high after sclk edge 0.5 t sl ns mosi 1 t hclk depends on the clock divider (cd) bits in the powcon mmr. t hclk = t uclk /2 cd . 2 t uclk = 48.8 ns. it corresponds to the 20.48 mhz internal clock from the pll before the clock divider. msb in bits[6:1] lsb in t dsu t dhd sclk (polarity = 0) ss sclk (polarity = 1) t sfs t ss t sh t sl t sr t sf t dav t df t dr miso lsb bits[6:1] msb 07474-004 figure 4. spi slave mode timingphase mode = 1
aduc7036 rev. b | page 13 of 132 table 5. spi slave mode timing (phase mode = 0) parameter description min typ max unit t ss ss to sclk edge 0.5 t sl ns t sl sclk low pulse width 1 (spidiv + 1) t hclk ns t sh sclk high pulse width 1 (spidiv + 1) t hclk ns t dav data output valid after sclk edge 1 , 2 (3 t uclk ) + (2 t hclk ) ns t dsu data input setup time before sclk edge 0 ns t dhd data input hold time after sclk edge 1 , 2 4 t uclk ns t df data output fall time 3.5 ns t dr data output rise time 3.5 ns t sr sclk rise time 3.5 ns t sf sclk fall time 3.5 ns t docs data output valid after ss edge 2 (3 t uclk ) + (2 t hclk ) ns t sfs ss high after sclk edge 0.5 t sl ns 1 t hclk depends on the clock divider (cd) bits in the powcon mmr. t hclk = t uclk /2 cd . 2 t uclk = 48.8 ns. it corresponds to the 20.48 mhz internal clock from the pll before the clock divider. sclk (polarity = 0) ss sclk (polarity = 1) t sh t sl t sr t sf t sfs mosi msb in bits[6:1] lsb in t dsu t dhd t dav miso lsb bits[6:1] msb t df t dr t docs t ss 07474-005 figure 5. spi slave mode timingphase mode = 0
aduc7036 lin timing specifications rev. b | page 14 of 132 transmit (input to transmitting node) v sup (transceiver supply of transmitting node) rxd (output of receiving node 1) rxd (output of receiving node 2) recessive th rec (max) t lin_dom (max) t lin_rec (min) t lin_dom (min) t lin_rec (max) th dom (max) th rec (min) th dom (min) dominant thresholds of receiving node 1 lin bus thresholds of receiving node 2 t bit t bit t bit t rx_pdr t rx_pdr t rx_pdf t rx_pdf 07474-006 figure 6. lin 2.0 timing specification
aduc7036 rev. b | page 15 of 132 absolute maximum ratings t a = ?40c to +115c, unless otherwise noted. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 6. parameter rating agnd to dgnd to vss to io_vss ?0.3 v to +0.3 v vbat to agnd ?22 v to +40 v vdd to vss ?0.3 v to +33 v vdd to vss for 1 sec ?0.3 v to +40 v lin to io_vss ?16 v to +40 v sti and wu to io_vss ?3 v to +33 v wake-up continuous current 50 ma high voltage i/o pins short-circuit current 100 ma digital i/o voltage to dgnd ?0.3 v to reg_dvdd + 0.3 v vref to agnd ?0.3 v to reg_avdd + 0.3 v adc inputs to agnd ?0.3 v to reg_avdd + 0.3 v esd human body model (hbm) rating hbm-adi0082 (based on ansi/esd stm5.1-2007). all pins except lin and vbat. 1 kv lin and vbat 6 kv iec 61000-4-2 for lin and vbat 7 kv storage temperature 125c junction temperature transient 150c continuous 130c lead temperature soldering reflow (15 sec) 260c esd caution
aduc7036 rev. b | page 16 of 132 13 14 15 16 17 18 19 20 21 22 23 24 vbat vref gnd_sw nc nc vtemp iin+ iin? agnd agnd nc reg_avdd 48 47 46 45 44 43 42 41 40 39 38 37 lin/bs pin configuration and fu nction descriptions d io_vss sti nc vss nc vdd wu nc nc nc xtal2 1 2 3 4 5 6 7 8 9 10 11 12 reset gpio_5/irq1/rxd gpio_6/txd gpio_7/irq4 gpio_8/irq5 tck tdi dgnd nc tdo ntrst tms notes 1. nc = no connect. 2. the exposed pad should be connected to dgnd. dgnd dgnd reg_dvdd nc gpio_4/eclk gpio_3/mosi gpio_2/miso gpio_1/sclk gpio_0/irq0/ss nc nc 35 xtal1 36 34 33 32 31 30 29 28 27 26 25 aduc7036 top view (not to scale) pin 1 indicator 07474-007 figure 7. pin configuration table 7. pin function descriptions pin no. mnemonic type 1 description 1 reset i reset input pin. active low. this pin has an internal, weak pull-up resistor to reg_dvdd and should be left unconnected when not in use. for added security and robustness, it is recommended that this pin be strapped via a resistor to reg_dvdd. 2 gpio_5/irq1/rxd i/o general-purpose digital i/o 5/external interrupt re quest 1/receive data for uart serial port. by default and after a power-on reset, this pin configures as an input. the pin has an internal, weak pull-up resistor and should be left unconnected when not in use. 3 gpio_6/txd i/o general-purpose digital i/o 6/transmit data for uart serial port. by default and after a power- on reset, this pin configures as an input. th e pin has an internal, weak pull-up resistor and should be left unconnected when not in use. 4 gpio_7/irq4 i/o general-purpose digital i/o 7/external interrup t request 4. by default and after a power-on reset, this pin configures as an input. the pin has an internal, weak pull-up resistor and should be left unconnected when not in use. 5 gpio_8/irq5 i/o general-purpose digital i/o 8/external interrup t request 5. by default and after a power-on reset, this pin configures as an input. the pin has an internal, weak pull-up resistor and should be left unconnected when not in use. 6 tck i jtag test clock. this clock input pin is one of the standard 5-pin jtag debug ports on the part. tck is an input pin only and has an internal, weak pull-up resistor. this pin is left unconnected when not in use. 7 tdi i jtag test data input. this data input pin is on e of the standard 5-pin jtag debug ports on the part. tdi is an input pin only and has an internal, weak pull-up resistor. this pin can be left unconnected when not in use. 8, 34, 35 dgnd s ground reference for on-chip digital circuits. 9, 16, 17, 23, 25, 26, 32, 38 to 40, 43, 45 nc no connect. these pins are not internally conne cted and are reserved for possible future use. therefore, do not externally connect these pins. these pins can be grounded, if required. 10 tdo o jtag test data output. this da ta output pin is one of the standard 5-pin jtag debug ports on the part. tdo is an output pin only. at power-on, this output is disabled and pulled high via an internal, weak pull-up resistor. this pin is left unconnected when not in use.
aduc7036 rev. b | page 17 of 132 pin no. mnemonic type 1 description 11 ntrst i jtag test reset. this reset input pin is one of the standard 5-pin jtag debug ports on the part. ntrst is an input pin only and has an internal, weak pull-down resistor. this pin remains unconnected when not in use. nt rst is also monitored by the on-chip kernel to enable lin boot load mode. 12 tms i jtag test mode select. this mode select input pin is one of the standard 5-pin jtag debug ports on the part. tms is an input pin only and has an internal, weak pull-up resistor. this pin is left unconnected when not in use. 13 vbat i battery voltage input to resistor divider. 14 vref i external reference input terminal. when this inp ut is not used, connect it directly to the agnd system ground. it can also be left unconnected. 15 gnd_sw i switch to internal analog ground reference. th is pin is the negative input for the external temperature channel and external reference. when this input is not used, connect it directly to the agnd system ground. 18 vtemp i external pin for ntc/ptc temperature measurement. 19 iin+ i positive differential input for current channel. 20 iin? i negative differential input for current channel. 21, 22 agnd s ground reference for on-chip precision analog circuits. 24 reg_avdd s nominal 2.6 v output from on-chip regulator. 27 gpio_0/irq0/ ss i/o general-purpose digital i/o 0/external interrupt request 0/slave select input for spi interface. by default and after power-on reset, this pin is configured as an input. the pin has an internal, weak pull-up resistor and should be left unconnected when not in use. 28 gpio_1/sclk i/o general-purpose digital i/o 1/serial clock input for spi interface. by default and after a power- on reset, this pin is configured as an input. the pin has an internal, weak pull-up resistor and should be left unconnected when not in use. 29 gpio_2/miso i/o general-purpose digital i/o 2/master input, slave output for spi interface. by default and after a power-on reset, this pin is configured as an input. the pin has an internal, weak pull-up resistor and should be left unconnected when not in use. 30 gpio_3/mosi i/o general-purpose digital i/o 3/master output, slave input for spi interface. by default and after a power-on reset, this pin is configured as an input. the pin has an internal, weak pull-up resistor and should be left unconnected when not in use. 31 gpio_4/eclk i/o general-purpose digital i/o 4/2.56 mhz clock output. by default and after a power-on reset, this pin is configured as an input. the pin has an internal, weak pull-up resistor and should be left unconnected when not in use. 33 reg_dvdd s nominal 2.6 v output from the on-chip regulator. 36 xtal1 o crystal oscillator output. if an external cr ystal is not used, this pin is left unconnected. 37 xtal2 i crystal oscillator input. if an external crystal is not used, connect this pin to the dgnd system ground. 41 wu i/o high voltage wake-up pin. this high voltage i/o pin has an internal, 10 k pull-down resistor and a high-side driver to vdd. if this pin is not being used, it should not be connected externally. 42 vdd s battery power supply to on-chip regulator. 44 vss s ground reference. this is the ground reference for the internal voltage regulators. 46 sti i/o high voltage serial test interface output pin. if th is pin is not used, externally connect it to the io_vss ground reference. 47 io_vss s ground reference for high voltage i/o pins. 48 lin/bsd i/o local interconnect network i/o/bit serial device i/o. this is a high voltage pin. epad exposed pad the exposed pad should be connected to dgnd. 1 i = input, o = output, i/o = input/output, s = supply.
aduc7036 rev. b | page 18 of 132 ?40 ?10 20 50 80 115 140 temperature (c) typical performance characteristics 0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 4 6 8 10 12 14 16 18 20 offset (v) vdd (v) 0 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 offset (v) core off 07474-008 vdd = 4v vdd = 18v cd = 0 cd = 1 07474-010 figure 8. adc current channel offs et vs. temperature, 10 mhz mcu 0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 offset (v) 20 07474-009 4 6 8 1012141618 vdd (v) +115c +25c ?40c figure 9. adc current channel offset vs. vdd, 10 mhz mcu figure 10. adc current channel offset vs. vdd @ 25c
aduc7036 rev. b | page 19 of 132 terminology conversion rate the conversion rate specifies the rate at which an output result is available from the adc after the adc has settled. the - conversion techniques used on this part mean that while the adc front-end signal is oversampled at a relatively high sample rate, a subsequent digital filter is used to decimate the output, providing a valid 16-bit data conversion result for output rates from 1 hz to 8 khz. note that when software switches from one input to another on the same adc, the digital filter must first be cleared and then allowed to average a new result. depending on the configuration of the adc and the type of filter, this may require multiple conversion cycles. integral nonlinearity (inl) inl is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. the end- points of the transfer function are zero scale, a point ? lsb below the first code transition, and full scale, a point ? lsb above the last code transition (111...110 to 111...111). the error is expressed as a percentage of full scale. no missing codes no missing codes is a measure of the differential nonlinearity of the adc. the error is expressed in bits (as 2 n bits, where n is no missing codes) and specifies the number of codes (adc results) that are guaranteed to occur through the full adc input range. offset error offset error is the deviation of the first code transition adc input voltage from the ideal first code transition. offset error drift offset error drift is the variation in absolute offset error with respect to temperature. this error is expressed as lsbs per degrees celsius. gain error gain error is a measure of the span error of the adc. it is a measure of the difference between the measured and the ideal span between any two points in the transfer function. output noise the output noise is specified as the standard deviation (that is, 1 ) of the distribution of adc output codes that are collected when the adc input voltage is at a dc voltage. it is expressed as microvolts rms (v rms). the output, or rms noise, can be used to calculate the effective resolution of the adc as defined by the following equation: effective resolution = log 2 ( full-scale range/rms noise ) where effective resolution is expressed in bits. the peak-to-peak noise is defined as the deviation of codes that fall within 6.6 of the distribution of adc output codes that are collected when the adc input voltage is at dc. the peak-to- peak noise is therefore calculated as 6.6 times the rms noise. the peak-to-peak noise can be used to calculate the adc (noise-free code) resolution for which there is no code flicker within a 6.6 limit, as defined by the following equation: noise-free code resolution = log 2 ( full-scale range / peak-to- peak noise ) where noise-free code resolution is expressed in bits.
aduc7036 rev. b | page 20 of 132 theory of operation the aduc7036 is a complete system solution for battery moni- toring in 12 v automotive applications. these devices integrate all of the required features to precisely and intelligently monitor, process, and diagnose 12 v battery parameters, including battery current, voltage, and temperature, over a wide range of operating conditions. minimizing external system components, the device is powered directly from the 12 v battery. an on-chip, low dropout regula- tor generates the supply voltage for two integrated, 16-bit, - adcs. the adcs precisely measure battery current, voltage, and temperature to characterize the state of the health and charge of the car battery. a flash/ee memory-based arm7? microcontroller (mcu) is also integrated on chip. it is used to both preprocess the acquired battery variables and to manage communications from the aduc7036 to the main electronic control unit (ecu) via a local interconnect network (lin) interface that is integrated on chip. both the mcu and the adc subsystem can be individually configured to operate in normal or flexible power saving modes of operation. in its normal operating mode, the mcu is clocked indirectly from an on-chip oscillator via the phase-locked loop (pll) at a maximum clock rate of 20.48 mhz. in its power saving oper- ating modes, the mcu can be totally powered down, waking up only in response to an adc conversion result ready event, a digital comparator event, a wake-up timer event, a por event, or an external serial communication event. the adc can be configured to operate in a normal (full power) mode of operation, interrupting the mcu after various sample conversion events. the current channel features two low power modeslow power and low power plusgenerating conversion results to a lower performance specification. on-chip factory firmware supports in-circuit flash/ee repro- gramming via the lin or jtag serial interface ports, and nonintrusive emulation is also supported via the jtag interface. these features are incorporated into a low cost quickstart? development system supporting the aduc7036. the aduc7036 operates directly from the 12 v battery supply and is fully specified over a temperature range of ?40c to +115c. the aduc7036 is functional, but with degraded performance, at temperatures from 115c to 125c. overview of the arm7tdmi core the arm7 core is a 32-bit, reduced instruction set computer (risc), developed by arm ltd. the arm7tdmi? is a von neumann-based architecture, meaning that it uses a single 32-bit bus for instruction and data. the length of the data can be eight, 16, or 32 bits, and the length of the instruction word is either 16 bits or 32 bits, depending on the mode in which the core is operating. the arm7tdmi is an arm7 core with four additional features, as listed in table 8 . table 8. arm7tdmi feature description t support for the thumb? (16-bit) instruction set d support for debug m enhanced multiplier i includes the embeddedice? module to support embedded system debugging thumb mode (t) an arm instruction is 32 bits long. the arm7tdmi processor supports a second instruction set compressed into 16 bits, the thumb instruction set. faster code execution from 16-bit memory and greater code density can be achieved by using the thumb instruction set, making the arm7tdmi core particularly well-suited for embedded applications. h owever, the thumb mode has three limitations. ? relative to arm, the thumb code usually requires more instructions to perform a task. therefore, arm code is best for maximizing the performance of time-critical code in most applications. ? the thumb instruction set does not include some instructions that are needed for exception handling, so arm code may be required for exception handling. ? when an interrupt occurs, the core vectors to the interrupt location in memory and executes the code present at that address. the first command is required to be in arm code. multiplier (m) the arm7tdmi instruction set includes an enhanced multiplier with four extra instructions to perform 32-bit by 32-bit multiplication with a 64-bit result, or 32-bit by 32-bit multiplication-accumulation (mac) with a 64-bit result. embeddedice (i) the embeddedice module provides integrated on-chip debug support for the arm7tdmi. the embeddedice module contains the breakpoint and watchpoint registers that allow nonintrusive user code debugging. these registers are con- trolled through the jtag test port. when a breakpoint or watchpoint is encountered, the processor halts and enters the debug state. once in a debug state, the processor registers can be interrogated, as can the flash/ee, sram, and memory mapped registers.
aduc7036 rev. b | page 21 of 132 arm7 exceptions t he arm7 supports five types of exceptions with a privileged processing mode associated with each type. the five types of exceptions are as follows: ? normal interrupt or irq. this is provided to service general-purpose interrupt handling of internal and external events. ? fast interrupt or fiq. this is provided to service data transfer or a communication channel with low latency. fiq has priority over irq. ? memory abort (prefetch and data). ? attempted execution of an undefined instruction. ? software interrupt (swi) instruction that can be used to make a call to an operating system. typically, the programmer defines interrupts as irq, but for higher priority interrupts, the programmer can define interrupts as the fiq type. the priority of these exceptions and vector address are listed in table 9 . table 9. exception priorities and vector addresses priority exception address 1 hardware reset 0x00 2 memory abort (data) 0x10 3 fiq 0x1c 4 irq 0x18 5 memory abort (prefetch) 0x0c 6 software interrupt 1 0x08 6 undefined instruction 1 0x04 1 a software interrupt and an undefined instruction exception have the same priority and are mutually exclusive. the list of exceptions in tabl e 9 are located from 0x00 to 0x1c, with a reserved location at 0x14. this location is required to be written with either 0x27011970 or the checksum of page 0, excluding location 0x14. if this is not done, user code does not execute and lin download mode is entered. arm registers the arm7tdmi has 16 standard registers. r0 to r12 are used for data manipulation, r13 is the stack pointer, r14 is the link register, and r15 is the program counter that indicates the instruction currently being executed. the link register contains the address from which the user has branched (if the branch and link command was used) or the command during which an exception occurred. the stack pointer contains the current location of the stack. as a general rule, on an arm7tdmi, the stack starts at the top of the available ram area and descends using the area as required. a separate stack is defined for each of the exceptions. the size of each stack is user configurable and is dependent on the target application. on the aduc7036, the stack begins at 0x00040ffc and descends. when programming using high level languages, such as c, it is necessary to ensure that the stack does not overflow. this is dependent on the performance of the compiler that is used. when an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. all exception modes have replacement banked registers for the stack pointer (r13) and the link register (r14) as represented in figure 11 . the fiq mode has more registers (r8 to r12) supporting faster interrupt processing. with the increased number of noncritical registers, the interrupt can be processed without the need to save or restore these registers, thereby reducing the response time of the interrupt handling process. more information relative to the model of the programmer and the arm7tdmi core architecture can be found in arm7tdmi technical and arm architecture manuals available directly from arm ltd. r0 usable in user mode r1 system modes only r2 r3 r4 r5 r6 spsr_und spsr_irq spsr_abt spsr_svc r7 r8_fiq r8 r9_fiq r9 r10_fiq r10 r11_fiq r13_und r12_fiq r13_fiq r14_fiq r13_irq r11 r14_und r13_abt r12 r13 r14 r15 (pc) r14_irq r13_svc r14_abt r14_svc spsr_fiq cpsr user mode fiq mode svc mode abort mode irq mode undefined mode 07474-011 figure 11. regist er organization interrupt latency the worst-case latency for an fiq consists of the longest possible time for the request to pass through the synchronizer, for the longest instruction to complete (the longest instruction is an ldm) and load all the registers including the pc, and for the data abort entry and the fiq entry to complete. at the end of this time, the arm7tdmi executes the instruction at address 0x1c (the fiq interrupt vector address). the maximum fiq latency is 50 pro- cessor cycles or just over 2.44 s in a system using a continuous 20.48 mhz processor clock. the maximum irq latency calculation is similar but must allow for the fact that fiq has higher priority and may delay entry into the irq handling routine for an arbitrary length of time. this time can be reduced to 42 cycles if the ldm command is not used; some compilers have an option to compile without using this command. another option is to run the part in thumb mode, which reduces the time to 22 cycles.
aduc7036 rev. b | page 22 of 132 the minimum latency for fiq or irq interrupts is five cycles. this consists of the shortest time the request can take through the synchronizer plus the time to enter the exception mode. 0xffff0fff 0xffff0000 mmrs note that the arm7tdmi initially (first instruction) runs in arm (32-bit) mode when an exception occurs. the user can immediately switch from arm mode to thumb mode if required, for example, when executing interrupt service routines. memory organization t he arm7 mcu core, which has a von neumann-based architecture, sees memory as a linear array of 2 32 byte locations. as shown in figure 13 , the aduc7036 maps this into four distinct user areas: a memory area that can be remapped, an sram area, a flash/ee area, and a memory mapped register (mmr) area. ? the first 94 kb of this memory space is used as an area into which the on-chip flash/ee or sram can be remapped. ? the aduc7036 features a second 4 kb area at the top of the memory map used to locate the mmrs, through which all on-chip peripherals are configured and monitored. ? the aduc7036 features an sram size of 6 kb. ? the aduc7036 features 96 kb of on-chip flash/ee memory, 94 kb of which are available to the user and 2 kb of which are reserved for the on-chip kernel. any access, either a read or a write, to an area not defined in the memory map results in a data abort exception. memory format the aduc7036 memory organization is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest byte address. bit 31 byte 2 a . . . byte 3 b . . . byte 1 9 . . . byte 0 8 . . . bit 0 0xffffffff 0x00000004 0x00000000 6 2 7 3 5 1 4 0 32 bits 0 7474-012 figure 12. little endian format 0x00417ff 0x00040000 0x00097fff 0x00080000 flash/ee sram 0x0017fff 0x00000000 remappable memory space (flash/ee or sram) reserved reserved reserved reserved 7474-013 0 figure 13. memory map sram the aduc7036 features 6 kb of sram, organized as 1536 32 bits, that is, 1536 words located at 0x00040000. the ram space can be used as data memory and also as a volatile program space. arm code can run directly from sram at full clock speed because the sram array is configured as a 32-bit-wide memory array. sram is readable/writeable in 8-, 16-, and 32-bit segments. remap the arm exception vectors are situated at the bottom of the memory array, from address 0x00000000 to address 0x00000020. by default, after a reset, the flash/ee memory is logically mapped to address 0x00000000. it is possible to logically remap the sram to address 0x00000000. this is accomplished by setting bit 0 of the sysmap0 mmr located at 0xffff0220. to revert flash/ee to 0x00000000, bit 0 of sysmap0 is cleared. it may be desirable to remap ram to 0x00000000 to optimize the interrupt latency of the aduc7036 because code can run in full 32-bit arm mode and at maximum core speed. it should be noted that when an exception occurs, the core defaults to arm mode.
aduc7036 rev. b | page 23 of 132 remap operation when a reset occurs on the aduc7036, execution starts automatically in the factory-programmed internal configuration code. this so-called kernel is hidden and cannot be accessed by user code. if the aduc7036 is in normal mode, it executes the power-on configuration routine of the kernel and then jumps to the reset vector, address 0x00000000, to execute the reset exception routine of the user. because the flash/ee is mirrored at the bottom of the memory array at reset, the reset routine must always be written in flash/ee. the remap command must be executed from the absolute flash/ee address and not from the mirrored, remapped segment of memory, which may be replaced by sram. if a remap operation is executed while operating code from the mirrored location, prefetch/data aborts may occur or the user may observe abnormal program operation. any kind of reset remaps the flash/ee memory to the bottom of the memory array. sysmap0 register name: sysmap0 address: 0xffff0220 default value: updated by the kernel access: read/write access function: this 8-bit register allows user code to remap either ram or flash/ee space into the bottom of the arm memory space, starting at address 0x00000000. table 10. sysmap0 mmr bit designations bit description 7 to 1 reserved. these bits are reserved and should be written as 0 by user code. 0 remap bit. set by the user to remap the sram to 0x00000000. cleared automatically after a reset to remap the flash/ee memory to 0x00000000.
aduc7036 rev. b | page 24 of 132 reset there are four kinds of resets: external reset, power-on reset, watchdog reset, and software reset. the rststa register indicates the source of the last reset and can be written to by user code to initiate a software reset event. the bits in this register can be cleared to 0 by writing to the rstclr mmr at 0xffff0234. the bit designations in rstclr mirror those of rststa. these registers can be used during a reset exception service routine to identify the source of the reset. the implications of all four kinds of reset events are shown in table 12 . rststa register name: rststa address: 0xffff0230 default value: varies according to type of reset (see tabl e 11 ) access: read/write access function: this 8-bit register indicates the source of the last reset event and can be written to by user code to initiate a software reset. rstclr register name: rstclr address: 0xffff0234 access: write only function: this 8-bit, write only register clears the corresponding bit in rststa. table 11. rststa/rstclr mmr bit designations bit description 7 to 4 not used. these bits are no t used and always read as 0. 3 external reset. set automatically to 1 when an external reset occurs. cleared by setting the co rresponding bit in rstclr. 2 software reset. set to 1 by user code to generate a sofware reset. cleared by setting the co rresponding bit in rstclr. 1 1 watchdog timeout. set automatically to 1 when a watchdog timeout occurs. cleared by setting the co rresponding bit in rstclr. 0 power-on reset. set automatically when a power-on reset occurs. cleared by setting the co rresponding bit in rstclr. 1 if the software reset bit in rststa is set, any write to rstclr that does not clear this bit generates a software reset. table 12. device reset implications impact reset reset external pins to default state execute kernel reset all external mmrs (excluding rststa) reset all hv indirect registers reset peripherals reset watchdog timer valid ram 1 rststa status (after a reset event) por yes yes yes yes yes yes yes/no 2 rststa[0] = 1 watchdog yes yes yes yes yes no yes rststa[1] = 1 software yes yes yes yes yes no yes rststa[2] = 1 external pin yes yes yes yes yes no yes rststa[3] = 1 1 ram is not valid in the case of a reset following a lin download. 2 the impact on ram is dependent on the hvmon[3] contents if lvf is enabled. when lvf is enabled using hvcfg0[2], ram has not be en corrupted by the por mechanism if the lvf status bit, hvmon[3], is 1. see the low voltage flag (lvf) sect ion for more information.
aduc7036 rev. b | page 25 of 132 flash/ee memory the aduc7036 incorporates flash/ee memory technology on chip to provide the user with nonvolatile, in-circuit reprogram- mable memory space. like eeprom, flash memory can be programmed in-system at a byte level, although it must first be erased, with the erasure performed in page blocks. therefore, flash memory is often and more correctly referred to as flash/ee memory. overall, flash/ee memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit program- mability, high density, and low cost. incorporated within the aduc7036, flash/ee memory technology allows the user to update program code space in-circuit without the need to replace one-time programmable (otp) devices at remote operating nodes. the flash/ee memory is located at address 0x80000. upon a hard reset, the flash/ee memory maps to address 0x00000000. the factory-set default contents of all flash/ee memory locations is 0xff. flash/ee can be read in 8-, 16-, and 32-bit segments and written in 16-bit segments. the flash/ee is rated for 10,000 endurance cycles. this rating is based on the number of times that each byte is cycled, that is, erased and programmed. imple- menting a redundancy scheme in the software ensures that none of the flash locations reach 10,000 endurance cycles. the user can also write data variables to the flash/ee memory during run-time code execution, for example, for storing diagnostic battery parameter data. the entire flash/ee is available to the user as code and non- volatile data memory. there is no distinction between data and program space during arm code processing. the real width of the flash/ee memory is 16 bits, meaning that in arm mode (32-bit instruction), two accesses to the flash/ee are necessary for each instruction fetch. when operating at speeds of less than 20.48 mhz, the flash/ee memory controller can transparently fetch the second 16-bit halfword (part of the 32-bit arm operation code) within a single core clock period. therefore, for speeds less than 20.48 mhz (that is, cd > 0), it is recommended to use arm mode. for 20.48 mhz operation (that is, cd = 0), it is recommended to operate in thumb mode. the page size of this flash/ee memory is 512 bytes. typically, it takes the flash/ee controller 20 ms to erase a page, regardless of cd. writing a 16-bit word at cd = 0, 1, 2, or 3 requires 50 s; at cd = 4 or 5, 70 s; at cd = 6, 80 s; and at cd = 7, 105 s. it is possible to write to a single 16-bit location only twice between erasures; that is, it is possible to walk bytes, not bits. if a location is written to more than twice, the contents of the flash/ee page may become corrupt. programming flash/ee memory in-circuit the flash/ee memory can be programmed in-circuit, using a serial download mode via the lin interface or the integrated jtag port. serial downloading (in-circuit programming) the aduc7036 facilitates code download via the lin/bsd pin. jtag access the aduc7036 features an on-chip jtag debug port to facilitate code downloading and debugging. aduc7036 flash/ee memory the total 96 kb of flash/ee is organized as 47,000 16 bits. of this total, 94 kb is designated as user space, and 2 kb is reserved for boot loader/kernel space. flash/ee control interface the access to and control of the flash/ee memory on the aduc7036 are managed by an on-chip memory controller. the controller manages the flash/ee memory as two separate blocks (block 0 and block 1). block 0 consists of the 32 kb of flash/ee memory that is mapped from address 0x00090000 to address 0x00097fff, including the 2 kb kernel space that is reserved at the top of this block. block 1 consists of the 64 kb of flash/ee memory that is mapped from address 0x00080000 to address 0x0008ffff. it should be noted that the mcu core can continue to execute code from one memory block while an active erase or program cycle is being carried out on the other block. if a command operates on the same block as the code currently executing, the core is halted until the command is complete. this also applies to code execution. u ser code, lin, and jtag programming use the flash/ee control interface, consisting of the following mmrs: ? feexsta (x = 0 or 1): read only register. reflects the status of the flash/ee control interface. ? feexmod (x = 0 or 1): sets the operating mode of the flash/ee control interface. ? feexcon (x = 0 or 1): 8-bit command register. the commands are interpreted as described in table 13 . ? feexdat (x = 0 or 1): 16-bit data register. ? feexadr (x = 0 or 1): 16-bit address register. ? feexsig (x = 0 or 1): holds the 24-bit code signature as a result of the signature command being initiated. ? feexhid (x = 0 or 1): protection mmr. controls read and write protection of the flash/ee memory code space. if previously configured via the feexpro register, feexhid may require a software key to enable access. ? feexpro (x= 0 or 1): a buffer of the feexhid register. stores the feexhid value and is automatically down- loaded to the feexhid registers on subsequent reset and power-on events. note that user software must ensure that the flash/ee controller completes any erase or write cycle before the pll is powered down. if the pll is powered down before an erase or write cycle is completed, the flash/ee page or byte may be corrupted.
aduc7036 rev. b | page 26 of 132 the fee0con and fee1con registers section to the fee0mod and fee1mod registers section provide detailed descriptions of the bit designations for each of the flash/ee control mmrs. fee0con and fee1con registers name: fee0con and fee1con address: 0xffff0e08 and 0xffff0e88 default value: 0x07 access: read/write access function: these 8-bit registers are written by user code to control the operating modes of the flash/ee memory controllers for block 0 (32 kb) and block 1 (64 kb). table 13. command codes in fee0con and fee1con code command description 1 0x00 2 reserved reserved. this command should not be written by user code. 0x01 2 single read load feexdat with th e 16-bit data indexed by feexadr. 0x02 2 single write write feexdat at the address po inted by feexadr. this operation takes 50 s. 0x03 2 erase write erase the page indexed by feexadr and write feexdat at the location pointed by feexadr. this operation takes 20 ms . 0x04 2 single verify compare the contents of the location po inted by feexadr to the data in feexda t. the result of the comparison is returned in feexsta, bit 1 or bit 0. 0x05 2 single erase erase the pa ge indexed by feexadr. 0x06 2 mass erase erase block 0 (32 kb) or block 1 (64 kb) of user space. the 2 kb kernel is protected. this operation takes 1.2 sec. to prevent accidental execution, a command sequence is required to execute this instruction (see the command sequence for executing a mass erase section). 0x07 default command. 0x08 reserved reserved. this command should not be written by user code. 0x09 reserved reserved. this command should not be written by user code. 0x0a reserved reserved. this command should not be written by user code. 0x0b signature fee0con: this command results in the generation of a 24-bi t linear feedback shift register (lfsr)-based signature that is loaded into fee0sig. if fee0adr is less than 0x97800, this command results in a 24-bit lfsr-based signature of the user code space from the page specified in fee0adr upwards, includin g the kernel, security bits, and flash/ee key. if fee0adr is greater than 0x97800, the kernel and manu facturing data are signed. this operation takes 120 s. fee1con: this command results in the generation of a 24-bit lfsr-based signature, beginning at fee1adr and ending at the end of the 63,500 block, that is loaded into f ee1sig. the last page of this block is not included in the sign generation. 0x0c protect this command can be run only once. the value of feexpr o is saved and can be removed only with a mass erase (0x06) or with the software protection key. 0x0d reserved reserved. this command should not be written by user code. 0x0e reserved reserved. this command should not be written by user code. 0x0f ping no operation, interrupt generated. 1 the x represents 0 or 1, designating flash/ee block 0 or block 1. 2 the fee0con register reads 0x07 immediat ely after the execution of this command.
aduc7036 rev. b | page 27 of 132 command sequence for executing a mass erase given the significance of the mass erase command, the following specific code sequence must be executed to initiate this operation: set bit 3 in feexmod. write 0xffc3 in feexadr. write 0x3cff in feexdat. run the mass erase command (code 0x06) in feexcon. this sequence is illustrated by the following example: int a = feexsta; // ensure feexsta is cleared feexmod = 0x08 feexadr = 0xffc3 feexdat = 0x3cff feexcon = 0x06; // mass erase command while (feexsta & 0x04){} //wait for command to finish it should be noted that to run the mass erase command via fee0con, the write protection on the lower 64 kb must be disabled. that is, fee1hid/fee1pro are set to 0xffffffff. this setting can be accomplished by first removing the protec- tion or by erasing the lower 64 kb. fee0sta and fee1sta registers name: fee0sta and fee1sta address: 0xffff0e00 and 0xffff0e80 default value: 0x20 access: read only function: these 8-bit, read only registers can be read by user code, and they reflect the current status of the flash/ee memory controllers. table 14. fee0sta and fee1 sta mmr bit designations bit description 1 7 to 4 not used. these bits are not used and always read as 0. 3 flash/ee interrupt status bit. set automatically when an interrupt occurs, that is, when a command is complete and the flash/ee interrupt enable bit in the feexmod register is set. cleared automatically when the feexsta register is read by user code. 2 flash/ee controller busy. set automatically when the flash/ee controller is busy. cleared automatically when the controller is not busy. 1 command fail. set automatically when a command written to feexcon completes unsuccessfully. cleared automatically when the feexsta register is read by user code. 0 command successful. set automatically by the mcu when a command is completed successfully. cleared automatically when the fee0sta register is read by user code. 1 the x represents 0 or 1, designating flash/ee block 0 or flash/ee block 1. fee0adr and fee1adr registers name: fee0adr and fee1adr address: 0xffff0e10 and 0xffff0e90 default value: 0x0000 (fee1adr). for fee0adr, see the system identification fee0adr section. access: read/write access function: these 16-bit registers dictate the address acted upon when a flash/ee command is executed via feexcon.
aduc7036 rev. b | page 28 of 132 fee0dat and fee1dat registers name: fee0dat and fee1dat address: 0xffff0e0c and 0xffff0e8c default value: 0x0000 access: read/write access function: this 16-bit register contains the data either read from or to be written to the flash/ee memory. fee0mod and fee1mod registers name: fee0mod and fee1mod address: 0xffff0e04 and 0xffff0e84 default value: 0x00 access: read/write access function: these registers are written by user code to configure the mode of operation of the flash/ee memory controllers. table 15. fee0mod and fee1mod mmr bit designations bit description 1 15 to 7 not used. these bits are reserved for future functionality and should be written as 0 by user code. 6, 5 flash/ee security lock bits. these bits must be written as [6:5] = 10 to complete the flash/ee security protect sequence. 4 flash/ee controller command complete interrupt enable. set to 1 by user code to enable the flash/ee controller to generate an interr upt upon completion of a flash/ee command. cleared to disable the generation of a flash/ee interrupt upon completion of a flash/ee command. 3 flash/ee erase/write enable. set by user code to enable the flash/ee erase and write access via feexcon. cleared by user code to disable the fl ash/ee erase and write access via feexcon. 2 reserved. should be written as 0. 1 flash/ee controller abort enable. set to 1 by user code to enable the flash/ee controller abort functionality. 0 reserved. should be written as 0. 1 the x represents 0 or 1, designating flash/ee block 0 or flash/ee block 1.
aduc7036 rev. b | page 29 of 132 flash/ee memory security the 94 kb of flash/ee memory available to the user can be read and write protected using the ffe0hid and fee1hid registers. in block 0, the fee0hid mmr protects the 30 kb. bits[0:28] of this register protect page 0 to page 57 from writing. each bit protects two pages, that is, 1 kb. bits[29:30] protect page 58 and page 59, respectively; that is, each bit write protects a single page of 512 bytes. the msb of this register (bit 31) protects block 0 from being read via jtag. the fee0pro register mirrors the bit definitions of the fee0hid mmr. the fee0pro mmr allows user code to lock the protect- tion or security configuration of the flash/ee memory so that the protection configuration is automatically loaded on subsequent power-on or reset events. this flexibility allows the user to set and test protection settings temporarily using the fee0hid mmr and, subsequently, lock the required protection configu- ration (using fee0pro) when shipping protection systems into the field. in block 1 (64 kb), the fee1hid mmr protects the 64 kb. bits[0:29] of this register protect page 0 to page 119 from writing. each bit protects four pages, that is, 2 kb. bit 30 protects page 120 to page 127; that is, bit 30 write protects eight pages of 512 bytes. the msb of this register (bit 31) protects flash/ee block 1 from being read via jtag. as with block 0, the fee1pro register mirrors the bit definitions of the fee1hid mmr. the fee1pro mmr allows user code to lock the protection or security configuration of the flash/ee memory so that the protection configuration is automatically loaded on subsequent power-on or reset events. there are three levels of protection: temporary protection, keyed permanent protection, and permanent protection. temporary protection temporary protection can be set and removed by writing directly into the feexhid mmr. this register is volatile and, therefore, protection is in place only while the part remains powered on. this protection is not reloaded after a power cycle. keyed permanent protection keyed permanent protection can be set via feexpro, which is used to lock the protection configuration. the software key used at the start of the required feexpro write sequence is saved once and must be used for any subsequent access of the feexhid or feexpro mmrs. a mass erase sets the key back to 0xffff but also erases the entire user code space. permanent protection permanent protection can be set via feexpro, in a manner similar to the way keyed permanent protection is set, with the only difference being that the software key used is 0xdeaddead. when the feexpro write sequence is saved, only a mass erase sets the key back to 0xffffffff. the mass erase also erases the entire user code space. s equence to write the key and set permanent protection 1. write feexpro corresponding to the pages to be protected. 2. write the new (user-defined) 32-bit key in feexadr, bits[31:16] and feexdat, bits[15:0]. 3. write bits[6:5] = 0x10 in feexmod. 4. run the write key command (code 0x0c) in feexcon. to remove or modify the protection, the same sequence can be used with a modified value of feexpro. the previous sequence for writing the key and setting permanent protection is illustrated in the following example sequence, which protects writing page 4 and page 5 of the flash/ee. int a = feexsta; //ensure feexsta is cleared feexpro =0 xfffffffb; //protect page 4 and page 5 feexadr = 0x66bb; //32-bit key value (bits[31:16]) feexdat = 0xaa55; //32-bit key value (bits[15:0]) feexmod = 0x0048 //lock security sequence feexcon = 0x0c; //write key command while (feexsta & 0x04){} //wait for command to finish
aduc7036 rev. b | page 30 of 132 block 0, flash/ee memory protection registers name: fee0hid and fee0pro address: 0xffff0e20 (for fee0hid) and 0xffff0e1c (for fee0pro) default value: 0xffffffff (for fee0hid) and 0x00000000 (for fee0pro) access: read/write access function: these registers are written by user code to configure the protection of the flash/ee memory. table 16. fee0hid and fee0 pro mmr bit designations bit description 1 31 read protection bit. set by user code to allow reading the 32 kb flash/ee block code via jtag read access. cleared by user code to protect the 32 kb flash/ee block code via jtag read access. 30 write protection bit. set by user code to allow writes to page 59. cleared by user code to write protect page 59. 29 write protection bit. set by user code to allow writes to page 58. cleared by user code to write protect page 58. 28 to 0 write protection bits. set by user code to allow writes to page 0 to page 57 of the 30 kb flash/ee code memory. each bit write protects two pages, and each page consists of 512 bytes. cleared by user code to write protect page 0 to page 57 of the 30 kb flash/ee code memory. each bit write protects two pages, a nd each page consists of 512 bytes. 1 the x represents 0 or 1, designating flash/ee block 0 or flash/ee block 1. block 1, flash/ee memory protection registers name: fee1hid and fee1pro address: 0xffff0ea0 (for fee1hid) and 0xffff0e9c (for fee1pro) default value: 0xffffffff (for fee1hid) and 0x00000000 (for fee1pro) access: read/write access function: these registers are written by user code to configure the protection of the flash/ee memory. table 17. fee1hid and fee1 pro mmr bit designations bit description 31 read protection bit. set by user code to allow reading of the 64 kb flash/ee block code via jtag read access. cleared by user code to read protect the 64 kb flash/ee block code via jtag read access. 30 write protection bit. write protects eigh t pages. each page consists of 512 bytes. set by user code to allow writes to page 120 to page 127 of the 64 kb flash/ee code memory. cleared by user code to write protect page 120 to page 127 of the 64 kb flash/ee code memory. 29 to 0 write protection bits. set by user code to allow writes to page 0 to page 119 of the 64 kb flash/ee code memory. each bi t write protects four pages, a nd each page consists of 512 bytes. cleared by user code to write protect page 0 to page 119 of th e 64 kb flash/ee code memory. each bit write protects two pages, and each page consists of 512 bytes.
aduc7036 rev. b | page 31 of 132 0 25 40 55 70 85 100 115 130 145 junction temperature (c) flash/ee memory reliability the flash/ee memory array on the part is fully qualified for two key flash/ee memory characteristics: flash/ee memory cycling endurance and flash/ee memory data retention. endurance quantifies the ability of the flash/ee memory to be cycled through many program, read, and erase cycles. a single endurance cycle is composed of four independent, sequential events, defined as initial page erase sequence, read/verify sequence, byte program sequence, and second read/verify sequence. in reliability qualification, every halfword (16-bit wide) location of the three pages (top, middle, and bottom) in the flash/ee memory is cycled 10,000 times from 0x0000 to 0xffff. as shown in table 1 , the flash/ee memory endurance qualification of the part is carried out in accordance with jedec retention lifetime specification a117 . the results allow the specification of a minimum endurance figure over supply and temperature of 10,000 cycles. retention quantifies the ability of the flash/ee memory to retain its programmed data over time. again, the part is qualified in accordance with the formal jedec retention lifetime specification a117 at a specific junction temperature (t j = 85c). as part of this qualification procedure, the flash/ee memory is cycled to its specified endurance limit, described previously, before data retention is characterized. this means that the flash/ee memory is guaranteed to retain its data for its fully specified retention lifetime every time the flash/ee memory is reprogrammed. in addition, note that retention lifetime, based on an activation energy of 0.6 ev, derates with t j as shown in figure 14 . 150 300 450 600 retention (years) 07474-014 figure 14. flash/ee memory data retention code execution time from sram and flash/ee this section describes sram and flash/ee access times during execution for applications where execution time is critical. execution from sram fetching instructions from sram takes one clock cycle because the access time of the sram is 2 ns, and a clock cycle is 49 ns minimum. however, when the instruction involves reading or writing data to memory, one extra cycle must be added if the data is in sram. if the data is in flash/ee, two cycles must be added: one cycle to execute the instruction and two cycles to retrieve the 32-bit data from flash/ee. a control flow instruction, such as a branch instruction, takes one cycle to fetch and two cycles to fill the pipeline with the new instructions. execution from flash/ee in thumb mode, where instructions are 16 bits, one cycle is needed to fetch any instruction. in arm mode, with cd = 0, two cycles are needed to fetch the 32-bit instructions. with cd > 0, no extra cycles are required for the fetch because the flash/ee memory continues to be clocked at full speed. in addition, some dead time is needed before accessing data for any value of cd bits. timing is identical in both modes when executing instructions that involve using the flash/ee for data memory. if the instruction to be executed is a control flow instruction, an extra cycle is needed to decode the new address of the program counter, and then four cycles are needed to fill the pipeline if cd = 0. a data processing instruction involving only the core register does not require any extra clock cycles. data transfer instructions are more complex and are summarized in tabl e 18 . table 18. typical execution cycles in arm/thumb mode instructions fetch cycles dead time data access ld 2/1 1 2 ldh 2/1 1 1 ldm/push 2/1 n 2 n str 2/1 1 2 50 s strh 2/1 1 50 s strm/pop 2/1 n 2 n 50 s with 1 < n 16, n is the number of data to load or store in the multiple load/store instruction. by default, flash/ee code execution is suspended during any flash/ee erase or write cycle. a page (512 bytes) erase cycle takes 20 ms and a write (16 bits) word command takes 50 s. however, the flash/ee controller allows erase/write cycles to be aborted if the arm core receives an enabled interrupt during the current flash/ee erase/write cycle. the arm7 can, therefore, imme- diately service the interrupt and then return to repeat the flash/ee command. the abort operation typically requires 10 clock cycles. if the abort operation is not feasible, the user can run flash/ee programming code and the relevant interrupt routines from sram, allowing the core to immediately service the interrupt.
aduc7036 rev. b | page 32 of 132 on-chip kernel t he aduc7036 features an on-chip kernel resident in the top 2 kb of the flash/ee code space. after any reset event, this kernel copies the factory-calibrated data from the manufacturing data space into the various on-chip peripherals. the peripherals calibrated by the kernel are as follows: ? power supply monitor (psm) ? p recision oscillator ? l ow power oscillator ? r eg_avdd/reg_dvdd ? l ow power voltage reference ? normal mode voltage reference ? current adc (offset and gain) ? voltage/temperature adc (offset and gain) u ser mmrs that can be modified by the kernel and differ from their por default values are as follows: ? r0 to r15 ? gp0con/gp2con ? syschk ? adcmde/adc0con ? fee0adr/fee0con/fee0sig ? hvdat/hvcon ? hvcfg0/hvcfg1 ? t3ld the aduc7036 also features an on-chip lin downloader. a flowchart of the execution of the kernel is shown in figure 15 . the current revision of the kernel can be derived from sysser1, as described in table 99 . after a por, the watchdog timer is disabled once the kernel code is exited. for the duration of the kernel execution, the watchdog timer is active with a timeout period of 500 ms. this ensures that when an error occurs in the kernel, the aduc7036 automatically resets. after any other reset, the watchdog timer maintains user code configuration for the period of the kernel and is refreshed just prior to kernel exit. a minimum watchdog period of 30 ms is required to allow correct lin downloader operation. if lin download mode is entered, the watchdog is periodically refreshed. normal kernel execution time, excluding lin download, is approximately 5 ms. it is possible to enter and leave lin download mode only through a reset. sram is not modified during normal kernel execution; rather, sram is modified during a lin download kernel execution. note that even with ntrst = 0, user code is not executed unless address 0x14 contains either 0x27011970 or the checksum of page 0, excluding address 0x14. if address 0x14 does not contain this information, user code is not executed and lin download mode is entered. during kernel execution, jtag access is disabled. with ntrst = 1, user code is always executed.
aduc7036 rev. b | page 33 of 132 initialize on-chip peripherals to factory- calibrated state flag page 0 error lin command jtag mode? ntrst = 1 key present? 0x14 = 0x27011970 page erased? 0x14 = 0xffffffff reset command checksum present? 0x14 = checksum e u xecute ser code no no no no no yes yes yes no yes yes 07474-015 figure 15. kernel flowchart
aduc7036 rev. b | page 34 of 132 memory mapped registers flash control interface the memory mapped register (mmr) space is mapped into the top 4 kb of the mcu memory space and accessed by indirect addressing, loading, and storage commands through the arm7 banked registers. an outline of the memory mapped register bank for the aduc7036 is shown in figure 16 . gpio spi the mmr space provides an interface between the cpu and all on-chip peripherals. all registers except the arm7 core registers (described in the arm registers section) reside in the mmr area. serial test interface as shown in table 19 to table 30 in the complete mmr listing section, the mmr data widths vary from one byte (eight bits) to four bytes (32 bits). the arm7 core can access any of the mmrs (single byte or multiple byte width registers) with a 32-bit read or write access. hv interface lin/bsd hardware uart the resultant read, for example, is aligned per little endian format, as described in the arm registers section. however, errors result if the arm7 core tries to access 4-byte (32-bit) mmrs with a 16-bit access. in the case of a 16-bit write access to a 32-bit mmr, the 16 most significant bits (the upper 16 bits) are written as 0s. the case of a 16-bit read access to a 32-bit mmr, only 16 of the mmr bits can be read. adc pll and oscillator control general-purpose timer4 watchdog timer3 wake-up timer2 general-purpose timer1 timer0 remap and system control interrupt controller 0xffffffff 0xffff1000 0xffff0e00 0xffff0d50 0xffff0d00 0xffff0a14 0xffff0a00 0xffff0894 0xffff0880 0xffff0810 0xffff0800 0xffff079c 0xffff0780 0xffff0730 0xffff0700 0xffff0580 0xffff0500 0xffff044c 0xffff0400 0xffff0394 0xffff0380 0xffff0370 0xffff0360 0xffff0350 0xffff0340 0xffff0334 0xffff0320 0xffff0318 0xffff0300 0xffff0244 0xffff0220 0xffff0110 0xffff0000 7474-016 0 figure 16. top-level mmr map
aduc7036 rev. b | page 35 of 132 complete mmr listing in table 19 to table 30 , addresses are listed in hexadecimal code. access types include r for read, w for write, and rw for read and write. table 19. irq address base = 0xffff0000 address name byte access type default value description 0x0000 irqsta 4 r 0x00000000 active irq source. see the interrupt system section and table 50 . 0x0004 irqsig 1 4 r n/a current state of all irq sources (enabled and disabled). see the interrupt system section and table 50 . 0x0008 irqen 4 rw 0x00000000 enabled irq sources. see the interrupt system section and table 50 . 0x000c irqclr 4 w n/a mmr to disable irq sources. see the interrupt system section and table 50 . 0x0010 swicfg 4 w n/a software interrupt configuration mmr. see the programmed interrupts section and table 51 . 0x0100 fiqsta 4 r 0x00000000 active irq source. see the interrupt system section and table 50 . 0x0104 fiqsig 1 4 r n/a current state of all irq sources (enabled and disabled). see the interrupt system section and table 50 . 0x0108 fiqen 4 rw 0x00000000 enabled irq sources. see the interrupt system section and table 50 . 0x010c fiqclr 4 w n/a mmr to disable irq sources. see the interrupt system section and table 50 . 1 depends on the level on the external interrupt pins (gpio_0, gpio_5, gpio_7, and gpio_8). table 20. system control address base = 0xffff0200 address name byte access type default value description 0x0220 sysmap0 1 rw n/a remap control register. see the remap operation section and table 10 . 0x0230 rststa 1 rw varies; depends on type of reset reset status mmr. see the reset section and table 11 and table 12 . 0x0234 rstclr 1 w n/a rststa clear mmr. see the reset section and table 11 and table 12 . 0x0238 sysser0 1 4 rw n/a system serial number 0. see the part identification section and table 98 for details. 0x023c sysser1 1 4 rw n/a system serial number 1. see the part identification section and table 99 for details. 0x0560 sysali 1 4 r n/a system assembly lot id. see the part identification section for details. 0x0240 syschk 1 4 rw n/a kernel checksum. see the system kernel checksum section. 1 updated by kernel. table 21. timer address base = 0xffff0300 address name byte access type default value description 0x0300 t0ld 2 rw 0x0000 timer0 load register. see the timer0lifetime timer and timer0 load register sections. 0x0304 t0val0 2 r 0x0000 timer0 value register 0. see the timer0lifetime timer and timer0 value registers sections. 0x0308 t0val1 4 r 0x00000000 timer0 value register 1. see the timer0lifetime timer and timer0 value registers sections. 0x030c t0con 4 rw 0x00000000 timer0 control mmr. see the timer0lifetime timer and timer0 control register sections. 0x0310 t0clri 1 w n/a timer0 interrupt clear register. see the timer0lifetime timer and timer0 load register sections. 0x0314 t0cap 2 r 0x0000 timer0 capture register. see the timer0lifetime timer and timer0 capture register sections. 0x0320 t1ld 4 rw 0x00000000 timer1 load register. see the timer1 and timer1 load register sections. 0x0324 t1val 4 r 0xffffffff timer1 value register. see the timer1 and timer1 value register sections. 0x0328 t1con 4 rw 0x01000000 timer1 control mmr. see the timer1 and timer1 control register sections. 0x032c t1clri 1 w n/a timer1 interrupt clear register. see the timer1 and timer1 clear register sections. 0x0330 t1cap 4 r 0x00000000 timer1 capture register. see the timer1 and timer1 capture register sections.
aduc7036 rev. b | page 36 of 132 address name byte access type default value description 0x0340 t2ld 4 rw 0x00000000 timer2 load register. see the timer2wake-up timer and timer2 load register sections. 0x0344 t2val 4 r 0xffffffff timer2 value register. see the timer2wake-up timer and timer2 value register sections. 0x0348 t2con 2 rw 0x0000 timer2 control mmr. see the timer2wake-up timer and timer2 control register sections and table 55 . 0x034c t2clri 1 w n/a timer2 interrupt clear register. see the timer2wake-up timer and timer2 clear register sections. 0x0360 t3ld 2 rw 0x0040 timer3 load register. see the timer3watchdog timer and timer3 load register sections. 0x0364 t3val 2 r 0x0040 timer3 value register. see the timer3watchdog timer and timer3 value register sections. 0x0368 t3con 2 rw 0x0000 timer3 control mmr. see the timer3watchdog timer , timer3 value register , and timer 3 control register sections and table 56 . 0x036c t3clri 1 1 w n/a timer3 interrupt clear register. see the timer3watchdog timer and timer3 clear register sections. 0x0380 t4ld 2 rw 0x0000 timer4 load register. see the timer4sti timer and timer4 load register sections. 0x0384 t4val 2 r 0xffff timer4 value register. see the timer4sti timer and timer4 value register sections. 0x0388 t4con 4 rw 0x00000000 timer4 control mmr. see the timer4sti timer and timer4 control register sections and table 57 . 0x038c t4clri 1 w n/a timer4 interrupt clear register. see the timer4sti timer and timer4 clear register sections. 0x0390 t4cap 2 r 0x0000 timer4 capture register. see the timer4sti timer section. 1 updated by kernel. table 22. pll base address = 0xffff0400 address name byte access type default value description 0x0400 pllsta 1 r n/a pll status mmr. see the pllsta register section and table 44 . 0x0404 powkey0 4 w n/a powcon prewrite key. see the powcon prewrite key section. 0x0408 powcon 1 rw 0x79 power control and core speed control register. see the powcon register section. 0x040c powkey1 4 w n/a powcon postwrite key. see the powcon postwrite key section. 0x0410 pllkey0 4 w n/a pllcon prewrite key. see the pllcon prewrite key section. 0x0414 pllcon 1 rw 0x00 pll clock source selection mmr. see the pllcon register section. 0x0418 pllkey1 4 w n/a pllcon postwrite key. see the pllcon postwrite key section. 0x042c osc0trm 1 rw 0xx8 low power oscillator trim bits mmr. see the osc0trm register section. 0x0440 osc0con 1 rw 0x00 low power oscillator calibration control mmr. see the osc0con register section. 0x0444 osc0sta 1 r 0x00 low power oscillator calibration status mmr. see the osc0sta register section. 0x0448 0sc0val0 2 r 0x0000 low power oscillator calibration counter 0 mmr. see the osc0val0 register section. 0x044c osc0val1 2 r 0x0000 low power oscillator calibration counter 1 mmr. see the osc0val1 register section.
aduc7036 rev. b | page 37 of 132 table 23. adc address base = 0xffff0500 address name byte access type default value description 0x0500 adcsta 2 r 0x0000 adc status mmr. see the adc status register section and table 35 . 0x0504 adcmski 1 rw 0x00 adc interrupt source enable mmr. see the adc interrupt mask register section. 0x0508 adcmde 1 rw 0x00 adc mode register. see the adc mode register section and table 36 . 0x050c adc0con 2 rw 0x0000 current adc control mmr. see the current channel adc control register section and table 37 . 0x0510 adc1con 2 rw 0x0000 v-/t-adc control mmr. see the voltage/temperature channel adc control register section and table 38 . 0x0518 adcflt 2 rw 0x0007 adc filter control mmr. see the adc filter register section and table 39 . 0x051c adccfg 1 rw 0x00 adc configuration mmr. see the adc configuration register section and table 42 . 0x0520 adc0dat 2 r 0x0000 current adc result mmr. see the current channel adc data register section. 0x0524 adc1dat 2 r 0x0000 v-adc result mmr. see the voltage channel adc data register section. 0x0528 adc2dat 2 r 0x0000 t-adc result mmr. see the temperature channel adc data register section. 0x0530 adc0of1 1 2 rw n/a current adc offset mmr. see the current channel adc offset calibration register section. 0x0534 adc1of 1 2 rw n/a voltage adc offset mmr. see the voltage channel adc offset calibration register section. 0x0538 adc2of 1 2 rw n/a temperature adc offset mmr. see the temperature channel adc offset calibration register section. 0x053c adc0gn 1 2 rw n/a current adc gain mmr. see the current channel adc gain calibration register section. 0x0540 adc1gn 1 2 rw n/a voltage adc gain mmr. see the voltage channel adc gain calibration register section. 0x0544 adc2gn 1 2 rw n/a temperature adc gain mmr. see the temperature channel adc gain calibration register section. 0x0548 adc0rcl 2 rw 0x0001 current adc result count limit. see the current channel adc result counter limit register section. 0x054c adc0rcv 2 r 0x0000 current adc result count value. see the current channel adc result count register section. 0x0550 adc0th 2 rw 0x0000 current adc result threshold. see the current channel adc threshold register section. 0x0554 adc0tcl 1 rw 0x01 current adc result threshold count limit. see the current channel adc threshold count limit register section. 0x0558 adc0thv 1 r 0x00 current adc result threshold count limit value. see the current channel adc threshold count register section. 0x055c adc0acc 4 r 0x00000000 current adc result accumulator. see the current channel adc accumulator register section. 0x057c adcref 1 2 rw n/a low power mode voltage reference scaling factor. see the low power voltage reference scaling factor section. 1 updated by kernel.
aduc7036 rev. b | page 38 of 132 table 24. uart base address = 0xffff0700 address name byte access type default value description 0x0700 comtx 1 w n/a uart transmit register. see the uart tx register section. comrx 1 r 0x00 uart receive register. see the uart rx register section. comdiv0 1 rw 0x00 uart standard baud rate generator divisor value 0. see the uart divisor latch register 0 section. 0x0704 comien0 1 rw 0x00 uart interrupt enable mmr 0. see the uart interrupt enable register 0 section and table 84 . comdiv1 1 rw 0x00 uart standard baud rate generator divisor value 1. see the uart divisor latch register 1 section. 0x0708 comiid0 1 r 0x01 uart interrupt identification 0. see the uart interrupt identification register 0 section and table 85 . 0x070c comcon0 1 rw 0x00 uart control register 0. see the uart control register 0 section and table 81 . 0x0710 comcon1 1 rw 0x00 uart control register 1. see the uart control register 1 section and table 82 . 0x0714 comsta0 1 r 0x60 uart status register 0. see the uart status register 0 section and table 83 . 0x072c comdiv2 2 rw 0x0000 uart fractional divider mmr. see the uart fractional divider register section and table 86 . table 25. lin hardware sync base address = 0xffff0780 address name byte access type default value description 0x0780 lhssta 4 r 0x00000000 lhs status mmr. see the lin hardware synchronization status register section and table 92 . 0x0784 lhscon0 2 rw 0x0000 lhs control mmr 0. see the lin hardware synchronization control register 0 section and table 93 . 0x0788 lhsval0 2 r 0x0000 lhs timer0 mmr. see the lin hardware synchronization timer0 register section. 0x078c lhscon1 1 rw 0x32 lhs control mmr 1. see the lin hardware synchronization control register 1 section and table 94 . 0x0790 lhsval1 2 rw 0x0000 lhs timer1 mmr. see the lin hardware synchronization break timer1 register section. 0x0794 lhscap 2 r 0x0000 lhs capture mmr. see the lin hardware synchronization capture register section. 0x0798 lhscmp 2 rw 0x0000 lhs compare mmr. see the lin hardware synchronization compare register section. table 26. high voltage interface base address = 0xffff0800 address name byte access type default value description 0x0804 hvcon 1 rw n/a high voltage interface control mmr. see the high voltage interface control register section and table 71 and table 72 . 0x080c hvdat 2 rw n/a high voltage interface data mmr. see the high voltage data register section and table 73 .
aduc7036 rev. b | page 39 of 132 table 27. sti base address = 0xffff0880 address name byte access type default value description 0x0880 stikey0 4 w n/a sticon prewrite key. see the serial test interface key0 register section. 0x0884 sticon 2 rw 0x0000 serial test interface control mmr. see the serial test interface control register section and table 91 . 0x0888 stikey1 4 w n/a sticon postwrite key. see the serial test interface key1 register section. 0x088c stidat0 2 rw 0x0000 sti data mmr 0. see the serial test interface data0 register section. 0x0890 stidat1 2 rw 0x0000 sti data mmr 1. see the serial test interface data1 register section. 0x0894 stidat2 2 rw 0x0000 sti data mmr 2. see the serial test interface data2 register section. table 28. spi base address = 0xffff0a00 address name byte access type default value description 0x0a00 spista 1 r 0x00 spi status mmr. see the spi status register section and table 90 . 0x0a04 spirx 1 r 0x00 spi receive mmr. see the spi receive register section. 0x0a08 spitx 1 w n/a spi transmit mmr. see the spi transmit register section. 0x0a0c spidiv 1 rw 0x1b spi baud rate select mmr. see the spi divider register section. 0x0a10 spicon 2 rw 0x0000 spi control mmr. see the spi control register section and table 89 . table 29. gpio base address = 0xffff0d00 address name byte access type default value description 0x0d00 gp0con 4 rw 0x11100000 gpio port0 control mmr. see the gpio port0 control register section and table 59 . 0x0d04 gp1con 4 rw 0x10000000 gpio port1 control mmr. see the gpio port1 control register section and table 60 . 0x0d08 gp2con 4 rw 0x01000000 gpio port2 control mmr. see the gpio port2 control register section and table 61 . 0x0d20 gp0dat 1 4 rw 0x000000xx gpio port0 data control mmr. see the gpio port0 data register section and table 62. 0x0d24 gp0set 4 w n/a gpio port0 data set mmr. see the gpio port0 set register section and table 65 . 0x0d28 gp0clr 4 w n/a gpio port0 data clear mmr. see the gpio port0 clear register section and table 68 . 0x0d30 gp1dat 1 4 rw 0x000000xx gpio port1 data control mmr. see the gpio port1 data register section and table 63. 0x0d34 gp1set 4 w n/a gpio port1 data set mmr. see the gpio port1 set register section and table 66 . 0x0d38 gp1clr 4 w n/a gpio port1 data clear mmr. see the gpio port1 clear register section and table 69 . 0x0d40 gp2dat 1 4 rw 0x000000xx gpio port2 data control mmr. see the gpio port2 data register section and table 64. 0x0d44 gp2set 4 w n/a gpio port2 data set mmr. see the gpio port2 set register section and table 67 . 0x0d48 gp2clr 4 w n/a gpio port2 data clear mmr. see the gpio port2 clear register section and table 70 . 1 depends on the level on the external gpio pins.
aduc7036 rev. b | page 40 of 132 table 30. flash/ee base address = 0xffff0e00 address name byte access type default value description 0x0e00 fee0sta 1 r 0x20 flash/ee status mmr. 0x0e04 fee0mod 1 rw 0x00 flash/ee control mmr. 0x0e08 fee0con 1 rw 0x07 flash/ee control mmr. see table 13 . 0x0e0c fee0dat 2 rw 0x0000 flash/ee data mmr. 0x0e10 fee0adr 2 rw nonzero flash/ee address mmr. 0x0e18 fee0sig 3 r 0xffffff flash/ee lfsr mmr. 0x0e1c fee0pro 4 rw 0x00000000 flash/ee protection mmr. see the flash/ee memory security section and table 16 . 0x0e20 fee0hid 4 rw 0xffffffff flash/ee protection mmr. see the flash/ee memory security section and table 16 . 0x0e80 fee1sta 1 r 0x20 flash/ee status mmr. 0x0e84 fee1mod 1 rw 0x00 flash/ee control mmr. 0x0e88 fee1con 1 rw 0x07 flash/ee control mmr. see table 13 . 0x0e8c fee1dat 2 rw 0x0000 flash/ee data mmr. 0x0e90 fee1adr 2 rw 0x0000 flash/ee address mmr. 0x0e98 fee1sig 3 r 0xffffff flash/ee lfsr mmr. 0x0e9c fee1pro 4 rw 0x00000000 flash/ee protection mmr. see the flash/ee memory security section and table 17 . 0x0ea0 fee1hid 4 rw 0xffffffff flash/ee protection mmr. see the flash/ee memory security section and table 17 .
aduc7036 rev. b | page 41 of 132 16-bit, - analog-to-digital converters the aduc7036 incorporates tw o independent - analog-to- digital converters (adcs): the current channel adc (i-adc) and the voltage/temperature channel adc (v-/t-adc). these precision measurement channels integrate on-chip buffering, a programmable gain amplifier, 16-bit, - modulators, and digital filtering for precise measurement of current, voltage, and temperature variables in 12 v automotive battery systems. current channel adc (i-adc) the i-adc converts battery current sensed through an external 100 ? shunt resistor. on-chip programmable gain means that the i-adc can be configured to accommodate battery current levels from 1 a to 1500 a. as shown in figure 17 , the i-adc employs a - conversion technique to attain 16 bits of no missing codes performance. the - modulator converts the sampled input signal into a digital pulse train whose duty cycle contains the digital infor- mation. a modified sinc3, programmable, low-pass filter is then used to decimate the modulator output data stream to give a valid 16-bit data conversion result at programmable output rates from 4 hz to 8 khz in normal mode and from 1 hz to 2 khz in low power mode. the i-adc also incorporates counter, comparator, and accu- mulator logic. this allows the i-adc result to generate an interrupt after a predefined number of conversions has elapsed or the i-adc result exceeds a programmable threshold value. a fast adc overrange feature is also supported. once enabled, a 32-bit accumulator automatically sums the 16-bit i-adc results. the time to a first valid (fully settled) result on the current channel is three adc conversion cycles with chop mode disabled and two adc conversion cycles with chop mode enabled.
aduc7036 rev. b | page 42 of 132 pga adc threshold adc result output format buf chop chop an alog input diagnostic current sources two 50a iin+ and iin? current sources. an vol vref/ alog input diagnostic tage source 136 voltage input. analog input programmable chopping the inputs are alternately reversed through the conversion cycle. - adc the - architecture ensures 16 bits no missing codes. output average as part of the chopping implementation, each data-word output from the filter is summed and averaged with its predecessor. adc fast overrange generates an adc interrupt if the current input is grossly overranged. adc accumulator accumulates the adc result. programmable gain amplifier the programmable gain amplifier allows eight bipolar input ranges from 2.3mv to 1.2v (int vref = +1.2v). - modulator the modulator provides a high frequency, 1-bit data stream (the output of which is also chopped) to the digital filter, the duty cycle of which represents the sampled analog input voltage. iin+ iin? vref/136 gnd r eg_avdd reg_avdd - adc - modulator programmable digital filter output average offset coefficient gain coefficient adc interrupt adc result accumulator adc result adc result counter threshold counter adc interrupt generator generates an adc result from any one of four sources. adc result counter counts adc results, generates an interrupt on counter overflow. threshold counter counts up if adc results > threshold; counts down/resets if adc result < threshold. generates an interrupt on counter overflow. buffer amplifier the buffer amplifier presents a high impedance input stage for the pga driving the - modulator. precision reference the internal 5ppm/c reference is routed to the adc by default. an external reference on the vref pin can also be selected. internal reference vref programmable digital filter the sinc3 filter removes quantization noise introduced by the modulator. the update rate and bandwidth of this filter are programmable via the adcflt mmr. digital comparator the adc result is compared to a preset threshold. output scaling the output word from the digital filter is scaled by the calibration coefficients before being provided as the conversion result. 07474-017 figure 17. current adc, top-level overview
aduc7036 rev. b | page 43 of 132 voltage/temperature channel adc (v-/t-adc) the voltage/temperature channel adc (v-/t-adc) converts additional battery parameters, such as voltage and temperature. the input to this channel can be multiplexed from one of three input sources: an external voltage, an external temperature sensor circuit, or an on-chip temperature sensor. as with the current channel adc (i-adc), the v-/t-adc employs an identical - conversion technique, including a modified sinc3 low-pass filter to provide a valid 16-bit data conversion result at programmable output rates from 4 hz to 8 khz. an external rc filter network is not required because this is internally implemented in the voltage channel. the external battery voltage (vbat) is routed to the adc input via an on-chip, high voltage (divide-by-24), resistive attenuator. the voltage attenuator buffers are automatically enabled when the voltage attenuator input is selected. the battery temperature can be derived through the on-chip temperature sensor or an external temperature sensor input. the time to a first valid (fully settled) result after an input channel switch on the voltage/temperature channel is three adc conversion cycles with chop mode disabled. this adc is again buffered but, unlike the current channel, has a fixed input range of 0 v to v ref on vtemp and 0 v to 28.8 v on vbat (assuming an internal 1.2 v reference). a top-level overview of this adc signal chain is shown in figure 18 . adc result output format chop - adc the - architecture ensures 16 bits of no missing codes. output average as part of the chopping implementation, each data-word output from the filter is summed and averaged with its predecessor. - modulator the modulator provides a high frequency, 1-bit data stream (the output of which is also chopped) to the digital filter, the duty cycle of which represents the sampled analog input voltage. - adc - modulator programmable digital filter output average offset coefficient gain coefficient adc interrupt generator generates an adc interrupt after a voltage or temperature conversion is completed. precision reference the internal 5ppm/c reference is routed to the adc by default. an external reference on the vref pin can also be selected. buf internal temperature buf chop mux internal reference vref programmable digital filter the sinc3 filter removes quantization noise introduced by the modulator. the update rate and bandwidth of this filter are programmable via the adcflt mmr. output scaling the output word from the digital filter is scaled by the calibration coefficients before being provided as the conversion result. vbat vtemp 45 ? 2 ? 1 ? adc interrupt to voltage or temperature data mmr differential attenuator divide-by-24 input attenuator buffer amplifiers the buffer amplifiers present a high impedance input stage for the analog input. analog input programmable chopping the inputs are alternately reversed through the conversion cycle. 07474-018 figure 18. voltage/temperature adc, top-level overview
aduc7036 rev. b | page 44 of 132 adc ground switch the aduc7036 features an integrated ground switch pin, gnd_sw (pin 15). this switch allows the user to dynamically disconnect ground from external devices and, instead, use either a direct connection to ground or a connection to ground using a 20 k resistor. this additional resistor can be used to reduce the number of external components required for an ntc circuit. the ground switch feature can be used for reducing power consumption on application-specific boards. an example application is shown in figure 19 . r ref reg_avdd vtemp ntc 20k? re vt g_avdd emp gnd_sw gnd_sw ntc 07474-019 20k ? gnd_sw adcmde[6] adccfg[7] 07474-020 figure 19. example external temperature sensor circuits figure 19 shows an external ntc used in two modes, with one using the internal 20 k resistor and the second showing a direct connection to ground via gnd_sw. adccfg[7] controls the connection of the ground switch to ground, and adcmde[6] controls gnd_sw resistance, as shown in figure 20 . figure 20. internal ground switch configuration the possible combinations of adccfg[7] and adcmde[6] are shown in table 31 . table 31. gnd_sw configuration adccfg[7] adcmde[6] gnd_sw 0 0 floating 0 1 floating 1 0 direct connection to ground 1 1 connected to ground via 20 k resistor adc noise performance tables table 32 , table 33 , and table 34 list the output rms noise in microvolts for some typical output update rates on the i-adc and v-/t-adc. the numbers are typical and are generated at a differential input voltage of 0 v. the output rms noise is specified as the standard deviation (or 1 ) of the distribution of adc output codes collected when the adc input voltage is at a dc voltage. it is expressed in microvolts rms (v rms). table 32. typical output rms noise of cu rrent channel adc in normal power mode adcflt data update rate adc input range 2.3 mv (512) 4.6 mv (256) 4.68 mv (128) 18.75 mv (64) 37.5 mv (32) 75 mv (16) 150 mv (8) 300 mv (4 1 ) 600 mv (2 1 ) 1.2 v (1 1 ) 0xbf1d 4 hz 0.040 v 0.040 v 0.043 v 0.045 v 0.087 v 0.175 v 0.35 v 0.7 v 1.4 v 2.8 v 0x961f 10 hz 0.060 v 0.060 v 0.060 v 0.065 v 0.087 v 0.175 v 0.35 v 0.7 v 1.4 v 2.8 v 0x007f 50 hz 0.142 v 0.142 v 0.144 v 0.145 v 0.170 v 0.305 v 0.380 v 0.7 v 2.3 v 2.8 v 0x0007 1 khz 0.620 v 0.620 v 0.625 v 0.625 v 0.770 v 1.310 v 1.650 v 2.520 v 7.600 v 7.600 v 0x0000 8 khz 2.000 v 2.000 v 2.000 v 2.000 v 2.650 v 4.960 v 8.020 v 15.0 v 55.0 v 55.0 v 1 the maximum absolute input voltage allowed is ?200 mv to +300 mv, relative to ground. table 33. typical output rms noise (referred to adc voltage attenuator input) of voltage channel adc adcflt data update rate 28.8 v adc input range 0xbf1d 4 hz 65 v 0x961f 10 hz 65 v 0x0007 1 khz 180 v 0x0000 8 khz 1600 v table 34. typical output rms no ise of temperature channel adc adcflt data update rate 0 v to 1.2 v adc input range 0xbf1d 4 hz 2.8 v 0x961f 10 hz 2.8 v 0x0007 1 khz 7.5 v 0x0000 8 khz 55 v
aduc7036 rev. b | page 45 of 132 adc mmr interface the adc is controlled and configured using several mmrs that are described in detail in the adc status register section to the low power voltage reference scaling factor section. all bits defined in the top eight msbs (bits[8:15]) of the adcsta mmr are used as flags only and do not generate interrupts. all bits defined in the lower eight lsbs (bits[0:7]) of this mmr are logic ored to produce a single adc interrupt to the mcu core. in response to an adc interrupt, user code should interrogate the adcsta mmr to determine the source of the interrupt. each adc interrupt source can be individually masked via the adcmski mmr described in the adc interrupt mask register section. all adc result ready bits are cleared by a read of the adc0dat mmr. if the current channel adc is not enabled, all adc result ready bits are cleared by a read of the adc1dat or adc2dat mmrs. to ensure that i-adc and v-/t-adc conversion data are synchronous, user code should first read the adc1dat mmr and then the adc0dat mmr. new adc conversion results are not written to the adcxdat mmrs unless the respective adc result ready bits are first cleared. the only exception to this rule is the data conversion result updates when the arm core is powered down. in this mode, adcxdat registers always contain the most recent adc conversion result, even though the ready bits have not been cleared. adc status register name: adcsta address: 0xffff0500 default value: 0x0000 access: read only function: this read only register holds general status information related to the mode of operation or current status of the adcs. table 35. adcsta mmr bit designations bit description 15 adc calibration status. set automatically in hardware to indicate that an adc calibration cycle has been completed. cleared after adcmde is written to. 14 adc temperature conversion error. set automatically in hardware to indicate that a temperature conversion overrange or underrange has occurred. the conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case. cleared when a valid (in-range) temperature conversion result is written to the adc2dat register. 13 adc voltage conversion error. set automatically in hardware to indicate that a voltage conver sion overrange or underrange has occurred. the conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case. cleared when a valid (in-range) voltage conversi on result is written to the adc1dat register. 12 adc current conversion error. set automatically in hardware to indicate that a current conversion overrange or underrange has occurred. the conversion result is clamped to negative full scale (underrange error) or positive full scale (overrange error) in this case. cleared when a valid (in-range) current conversion result is written to the adc0dat register. 11 to 5 not used. these bits are reserved for future fu nctionality and should not be monitored by user code. 4 current channel adc comparator threshold. valid only if the current channel adc comparator is enabled via the adccfg mmr. set by hardware if the absolute value of the i-adc conversion result exceeds the value written in the adc0th mmr. however, if t he adc threshold counter is used (adc0tcl), th is bit is set only when the specified numb er of i-adc conversions equals the value i n the adc0thv mmr. cleared automatically by hardware when reconfigur ing the adc or if the comparator is disabled. 3 current channel adc overrange bit. set by hardware if the overrange detect function is enab led via the adccfg mmr and the i-adc input is grossly (>30% approximate) over range. this bit is updated every 125 s. cleared by software only when adccfg[2] is cleared to disabl e the function, or the adc gain is changed via the adc0con mmr. 2 temperature conversion result ready bit. set by hardware, if the temperature channel adc is enabled, as s oon as a valid temperature conversion result is written in the temperature data register (adc2dat mmr). it is also set at the end of a calibration. cleared by reading either adc2dat or adc0dat. 1 voltage conversion result ready bit. set by hardware, if the voltage channel adc is enabled, as soon as a valid voltage conversion re sult is written in the voltage data register (adc1dat mmr). it is also set at the end of a calibration. cleared by reading either adc1dat or adc0dat. 0 current conversion result ready bit. set by hardware, if the current channel adc is enabled, as soon as a valid current conversion result is written in the current data register (adc0dat mmr). it is also set at the end of a calibration. cleared by reading adc0dat.
aduc7036 rev. b | page 46 of 132 adc interrupt mask register name: adcmski address: 0xffff0504 default value: 0x00 access: read/write function: this register allows the adc interrupt sources to be individually enabled. the bit positions in this register are the same as the lower eight bits in the adcsta mmr. if a bit is set by user code to 1, the respective interrupt is enabled. by default, all bit s are 0, meaning all adc interrupt sources are disabled. adc mode register name: adcmde address: 0xffff0508 default value: 0x00 access: read/write function: this 8-bit register configures the mode of operation of the adc subsystem. table 36. adcmde mmr bit designations bit description 7 not used. this bit is reserved for future function ality and should be written as 0 by user code. 6 20 k resistor select. set to 1 to select the 20 k resistor as shown in figure 20 . set to 0 to select the direct path to ground as shown in figure 20 (default). 5 low power mode reference select. set to 1 to enable the precision voltage reference in either lo w power mode or low power plus mode, thereby increasing current consumption. set to 0 to enable the low power voltage reference in ei ther low power mode or low power plus mode (default). 4 to 3 adc power mode configuration. 00 = adc normal mode. if enabled, the adc operates with normal current consumption yielding optimum electrical performance. 01 = adc low power mode. if enabled, the i-adc operates with reduced current consumption. this limitation in current consumption is achieved (at the expense of adc noise performanc e) by fixing the gain to 128 and using the on-chip low power (131 khz) oscillator to directly drive the adc circuits. 10 = adc low power plus mode. if enabled, the adc operates with re duced current consumption. in this mode, the gain is fixed to 512 and the current consumed is approximat ely 200 a more than the adc low power mode. the additional current consumed also ensures that the adc noise performance is be tter than that achieved in adc low power mode. 11 = not defined. 2 to 0 adc operation mode configuration. 000 = adc power-down mode. all adc circuits (including internal reference) are powered down. 001 = adc continuous conversion mode. in this mode, any enabled adc continuously converts. 010 = adc single conversion mode. in this mode, any enabled adc performs a single conversion. the adc enters idle mode when the single shot conversion is complete. a single conversion takes two to three adc clock cycles depending on the chop mode. 011 = adc idle mode. in this mode, the adc is fully powered on but is held in reset. 100 = adc self-offset calibration. in this mode, an offset cali bration is performed on any enabled adc using an internally generated 0 v. the calibration is carried out at the user prog rammed adc settings; therefore, as with a normal single adc conversion, it takes two to three adc conversion cycles before a fully settled calibration result is ready. the calibration res ult is automatically written to the adcxof mmr of the respective adc. the adc returns to idle mode and the calibration and conversion ready status bits are set at th e end of an offset calibration cycle. 101 = adc self-gain calibration. in this mode, a gain calibration against an internal reference voltage is performed on all ena bled adcs. a gain calibration is a two-stage process and takes twice th e time of an offset calibratio n. the calibration result is automatically written to the adcxgn mmr of the respective adc. the adc returns to idle mode, and the calibration and conversion ready status bits are set at the end of a gain calibration cycle. an adc self-gain calibration should only be carrie d out on the current channel adc. preprogrammed, factory calibration coefficients (download ed automatically from internal flash/ee) should be used for voltage temperature measurements. if an exte rnal ntc is used, an adc self-calibration should be performed on the temperature channel. 110 = adc system zero-scale calibration. in this mode, a zero-s cale calibration is performed on enabled adc channels against an external zero-scale voltage driven at the adc input pins. the calibration is carried out at th e user programmed adc settings; therefore, as with a normal, single adc conversion, it takes th ree adc conversion cycles before a fully settled calibration res ult is ready. 111 = adc system full-scale calibration. in this mode, a full-sc ale calibration is performed on enabled adc channels against an external full-scale voltage driven at the adc input pins.
aduc7036 rev. b | page 47 of 132 current channel adc control register name: adc0con address: 0xffff050c default value: 0x0000 access: read/write function: this 16-bit register is used to configure the i-adc. note that if the current adc is reconfigured via adc0con, the voltage adc and temperature adc are also reset. table 37. adc0con mmr bit designations bit description 15 current channel adc enable. set to 1 by user code to enable the i-adc. cleared to 0 to power down the i-adc and reset the respective adc ready bit in the adcsta mmr to 0. 14, 13 iin current source enable. 00 = current sources off. 01 = enables the 50 a current source on iin+. 10 = enables the 50 a current source on iin?. 11 = enables the 50 a current source on both iin? and iin+. 12 to 10 not used. these bits are reserved for future functionality and should be written as 0. 9 current channel adc output coding. set to 1 by user code to configur e i-adc output coding as unipolar. cleared to 0 by user code to configure i-adc output coding as twos complement. 8 not used. this bit is reserved for future functionality and should be written as 0. 7, 6 current channel adc input select. 00 = iin+, iin? are selected. 01 = iin?, iin? are selected. diagnostic, internal short configuration. 10 = v ref /136, 0 v, diagnostic, test voltage for gain settings 128. note that if (reg_avdd, agnd) divided-by-2 reference is selected, reg_avdd is used for vref in this mode. this leads to adc0dat scaled by 2. 11 = not defined. 5, 4 current channel adc reference select. 00 = internal, 1.2 v precision reference selected. in adc low power mode, the voltage reference selection is controlled by adcmde[5]. 01 = external reference inputs (vref, gnd_sw) selected. 10 = external reference inputs divided-by-2 (vref, gnd_sw)/2 selected, which allows an external reference up to reg_avdd. 11 = (reg_avdd, agnd) divided-by-2 selected. 3 to 0 current channel adc gain select. the nominal i-adc full-scale input voltage = (vref/gain). 0000 = i-adc gain of 1. 0001 = i-adc gain of 2. 0010 = i-adc gain of 4. 0011 = i-adc gain of 8. 0100 = i-adc gain of 16. 0101 = i-adc gain of 32. 0110 = i-adc gain of 64. 0111 = i-adc gain of 128. 1000 = i-adc gain of 256. 1001 = i-adc gain of 512. 1xxx = i-adc gain is undefined.
aduc7036 rev. b | page 48 of 132 voltage/temperature channel adc control register name: adc1con address: 0xffff0510 default value: 0x0000 access: read/write function: this 16-bit register is used to configure the v-/t-adc. note that when selecting the vbat attenuator input, the voltage attenuator buffers are automatically enabled. table 38. adc1con mmr bit designations bit description 15 voltage/temperature channel adc enable. set to 1 by user code to enable the v-/t-adc. cleared to 0 to power down the v-/t-adc. 14, 13 vtemp current source enable. 00 = current sources off. 01 = enables 50 a current source on vtemp. 10 = enables 50 a current source on gnd_sw. 11 = enables 50 a current source on both vtemp and gnd_sw. 12 to 10 not used. these bits are reserved for future fu nctionality and should not be modified by user code. 9 voltage/temperature channel adc output coding. set to 1 by user code to configur e v-/t-adc output coding as unipolar. cleared to 0 by user code to configure v-/t-adc output coding as twos complement. 8 not used. this bit is reserved for future function ality and should be written as 0 by user code. 7, 6 voltage/temperature channel adc input select. 00 = vbat/24, agnd. vbat attenuator selected. the high voltage buffers are enabled automatically in this configuration. 01 = vtemp, gnd_sw. external temperature input selected, conversion result written to adc2dat. 10 = internal sensor. internal temperature sensor input selected, conversion result written to adc2dat. the temperature gradient is 0.33 mv/c; this is only appl icable to the internal temperature sensor. 11 = internal short. shorted input. 5, 4 voltage/temperature channel adc reference select. 00 = internal, 1.2 v precision reference selected. 01 = external reference inputs (vref, gnd_sw) selected. 10 = external reference inputs divided-by-2 (vref, gnd_sw)/2 selected. this allows an external reference up to reg_avdd. 11 = (reg_avdd, agnd)/2 selected for the voltage channel. (reg_avdd, gnd_sw)/2 selected for the temperature channel. 3 to 0 not used. these bits are reserved for future func tionality and should not be written as 0 by user code.
aduc7036 rev. b | page 49 of 132 adc filter register name: adcflt address: 0xffff0518 default value: 0x0007 access: read/write function: this 16-bit register controls the speed and resolution of the on-chip adcs. note that if adcflt is modified, the current and voltage/temperature adcs are reset. table 39. adcflt mmr bit designations bit description 15 chop enable. set by the user to enable system chopping of all active adcs. when this bit is se t, the adc has very low offset errors and drift, but the adc output rate is reduced by a factor of three if af = 0 (see sinc3 de cimation factor, bits[6:0], in this table ). if af > 0, then the adc output update rate is the same with chop on or off. when chop is enabled, the settling time is two output periods. 14 running average. set by the user to enable a running-average-by-two function reducing adc noise. this function is automatically enabled when chopping is active. it is an optional feature when chopp ing is inactive, and if enabled (when chopping is inactive), does not reduce the adc output rate but does increase the settling time by one conversion period. cleared by the user to disable the running average function. 13 to 8 averaging factor (af). the values written to these bits are used to implement a programmable first-order sinc3 postfilter. the averaging factor can further reduce adc noise at the expense of output rate, as de scribed in bits[6:0], sinc3 decimation factor, in this table. 7 sinc3 modify. set by the user to modify the standa rd sinc3 frequency response to increase the filter stop-band rejection by approximately 5 db. this is achieved by inserting a second notch (notch2) a f notch2 = 1.333 f notch , where f notch is the location of the first notch in the response. 6 to 0 sinc3 decimation factor (sf). 1 the value (sf) written in these bits controls the oversampling (decimation factor) of the sinc3 filter. the output rate from the sinc3 filter is given by f adc = (512,000/ ([sf + 1] 64)) hz 2 , when the chop bit (bit 15, chop enable) = 0 and the averaging factor (af) = 0. this is valid for all sf values 125. for sf = 126, f adc is forced to 60 hz. for sf = 127, f adc is forced to 50 hz. for information on calculating the f adc for sf (other than 126 and 127) and af values, refer to table 40 . 1 due to limitations on the digital filter internal data path, th ere are some limitations on the combinations of the sinc3 decim ation factor (sf) and averaging factor (af) that can be used to generate a required adc output rate. this restriction limits the minimum adc up date in normal power mode to 4 hz or 1 hz in lower power mode. 2 in low power mode and low power plus mode , the adc is driven directly by the low po wer oscillator (131 kh z) and not 512 khz. a ll f adc calculations should be divided by 4 (approximately).
aduc7036 rev. b | page 50 of 132 table 40. adc conversion rates and settling times chop enabled averaging factor running average f adc t settling 1 no no no 64]1[ + sf 000,512 adc f 3 no no yes 64]1[ + sf 000,512 adc f 4 no yes no ] 000,512 af 3[64]1[ sf ++ adc f 1 no yes yes ]3[64]1[ 000,512 af sf ++ adc f 2 yes n/a n/a 3]3[64]1[ 000,512 +++ af sf adc f 2 1 an additional time of approximately 60 s per ad c is required before the first adc is available. table 41. allowable combinations of sf and af af range sf 0 1 to 7 8 to 63 0 to 31 yes yes yes 32 to 63 yes yes no 64 to 127 yes no no
aduc7036 rev. b | page 51 of 132 adc configuration register name: adccfg address: 0xffff051c default value: 0x00 access: read/write function: this 8-bit adc configuration mmr controls extended functionality related to the on-chip adcs. table 42. adccfg mmr bit designations bit description 7 analog ground switch enable. set to 1 by user software to connect the external gnd_sw pin (pin 15) to an internal analog ground reference point. this bit ca n be used to connect and disconnect external circuits and compon ents to ground under program control and, thereby, minimize dc current consumption when the external circui t or component is not used. this bit is us ed in conjunction with adcmde[6] to selec t a 20 k resistor to ground. cleared by user code to disconnect the external gnd_sw pin. 6, 5 current channel (32-bit) accumulator enable. 00 = accumulator disabled and reset to 0. the accumulator must be disabled for a full adc conversion (adcsta[0] set twice) before the accumulator can be reenabled to ensure that the accumulator is reset. 01 = accumulator active. positive current values are added to the accumulator total; the accumulator can overflow if allowed to run for >65,535 conversions. negative current values are subtracted from the accumulato r total; the accumulator is clamped to a minimum value of 0. 10 = accumulator active. positive current values are added to the accumulator total; the accumulator can over flow if allowed to run for >65,535 convers ions. the absolute values of negative current are subtracted from th e accumulator total; the accumulator in this mode continues to accumulate negatively, below 0. 11 = not defined. 4, 3 current channel adc comparator enable. 00 = comparator disabled. 01 = comparator active, interrupt asserted if absolute value of i-adc conversion result is |i| adc0th. 10 = comparator count mode active, interrupt asserted if absolute value of an i-adc conversion result is |i| adc0th for the number of adc0tcl conversions. a conversion value of |i| < adc0th resets the threshold counter value (adc0thv) to 0. 11 = comparator count mode active, interrupt asserted if absolute value of an i-adc conversion result is |i| adc0th for the number of adc0tcl conversions. a conversion value of |i| < adc0th decrements the threshold counter value (adc0thv) toward 0. 2 current channel adc overrange enable. set by user to enable a coarse comparator on the current chan nel adc. if the current reading is grossly (>30% approximate) overrange for the active gain setting, then the overrange bit in the adcsta mmr is set. the current must be outside this range for greater than 125 s for the flag to be set. this feature should not be used in adc l ow power mode. cleared by user code to disable the overrange feature. 1 not used. this bit is reserved for future function ality and should be written as 0 by user code. 0 current channel adc, result counter enable. set by user to enable the result count mo de. in this mode, an i-adc interrupt is ge nerated only when adc0rcv = adc0rcl. this allows the i-adc to continuously monitor current but only interrupt the mcu core after a defined number of conversions. the voltage/temperature adc also continues to convert if enabled, but again, only the last conversion result is available (intermed iate v-/t-adc conversion results are not stored) when the adc counter interrupt occurs.
aduc7036 rev. b | page 52 of 132 current channel adc data register name: adc0dat address: 0xffff0520 default value: 0x0000 access: read only function: this adc data mmr holds the 16-bit conversion result from the i-adc. the adc does not update this mmr if the adc0 conversion result ready bit (adcsta[0]) is set. a read of this mmr by the mcu clears all asserted ready flags (adcsta[2:0]). voltage channel adc data register name: adc1dat address: 0xffff0524 default value: 0x0000 access: read only function: this adc data mmr holds the 16-bit voltage conversion result from the v-/t-adc. the adc does not update this mmr if the voltage conversion result ready bit (adcsta[1]) is set. if i-adc is not active, a read of this mmr by the mcu clears all asserted ready flags (adcsta[2:1]). temperature channel adc data register name: adc2dat address: 0xffff0528 default value: 0x0000 access: read only function: this adc data mmr holds the 16-bit temperature conversion result from the v-/t-adc. the adc does not update this mmr if the temperature conversion result ready bit (adcsta[2]) is set. if i-adc and v-adc are not active, a read of this mmr by the mcu clears all asserted ready flags (adcsta[2]). a read of this mmr clears adcsta[2]. current channel adc offset calibration register name: adc0of address: 0xffff0530 default value: part specific, factory programmed access: read/write function: this adc offset mmr holds a 16-bit offset calibration coefficient for the i-adc. the register is configured at power- on with a factory default value. however, this register automati- cally overwrites if an offset calibration of the i-adc is initiated by the user via bits in the adcmde mmr. user code can write to this calibration register only if the adc is in idle mode. an adc must be enabled and in idle mode before being written to any offset or gain register. the adc must be in idle mode for at least 23 s. voltage channel adc offset calibration register name: adc1of address: 0xffff0534 default value: part specific, factory programmed access: read/write function: this offset mmr holds a 16-bit offset calibration coefficient for the voltage channel. the register is configured at power-on with a factory default value. however, this register is automatically overwritten if an offset calibration of the voltage channel is initiated by the user via bits in the adcmde mmr. user code can write to this calibration register only if the adc is in idle mode. an adc must be enabled and in idle mode before being written to any offset or gain register. the adc must be in idle mode for at least 23 s. temperature channel adc offset calibration register name: adc2of address: 0xffff0538 default value: part specific, factory programmed access: read/write function: this adc offset mmr holds a 16-bit offset calibration coefficient for the temperature channel. the register is configured at power-on with a factory default value. however, this register is automatically overwritten if an offset calibration of the temperature channel is initiated by the user via bits in the adcmde mmr. user code can write to this calibration register only if the adc is in idle mode. an adc must be enabled and in idle mode before being written to any offset or gain register. the adc must be in idle mode for at least 23 s. current channel adc gain calibration register name: adc0gn address: 0xffff053c default value: part specific, factory programmed access: read/write function: this gain mmr holds a 16-bit gain calibration coefficient for scaling the i-adc conversion result. the register is configured at power-on with a factory default value. however, this register is automatically overwritten if a gain calibration of the i-adc is initiated by the user via bits in the adcmde mmr. user code can write to this calibration register only if the adc is in idle mode. an adc must be enabled and in idle mode before being written to any offset or gain register. the adc must be in idle mode for at least 23 s.
aduc7036 rev. b | page 53 of 132 voltage channel adc gain calibration register name: adc1gn address: 0xffff0540 default value: part specific, factory programmed access: read/write function: this gain mmr holds a 16-bit gain calibration coefficient for scaling a voltage channel conversion result. the register is configured at power-on with a factory default value. however, this register is automatically overwritten if a gain calibration of the voltage channel is initiated by the user via bits in the adcmde mmr. user code can write to this calibration register only if the adc is in idle mode. an adc must be enabled and in idle mode before being written to any offset or gain register. the adc must be in idle mode for at least 23 s. temperature channel adc gain calibration register name: adc2gn address: 0xffff0544 default value: part specific, factory programmed access: read/write function: this gain mmr holds a 16-bit gain calibration coefficient for scaling a temperature channel conversion result. the register is configured at power-on with a factory default value. however, this register is automatically overwritten if a gain calibration of the temperature channel is initiated by the user via bits in the adcmde mmr. user code can write to this calibration register only if the adc is in idle mode. an adc must be enabled and in idle mode before being written to any offset or gain register. the adc must be in idle mode for at least 23 s. current channel adc result counter limit register name: adc0rcl address: 0xffff0548 default value: 0x0001 access: read/write function: this 16-bit mmr sets the number of conversions that are required before an adc interrupt is generated. by default, this register is set to 0x0001. the adc counter function must be enabled via the adc result counter enable bit in the adccfg mmr. current channel adc result count register name: adc0rcv address: 0xffff054c default value: 0x0000 access: read only function: this 16-bit, read only mmr holds the current number of i-adc conversion results. it is used in conjunction with adc0rcl to mask i-adc interrupts, generating a lower interrupt rate. when adc0rcv = adc0rcl, the value in adc0rcv resets to 0 and recommences counting. it can also be used in conjunction with the accumulator (adc0acc) to allow an average current calculation to be undertaken. the result counter is enabled via adccfg[0]. this mmr is also reset to 0 when the i-adc is reconfigured, that is, when the adc0con or adcmde is written. current channel adc threshold register name: adc0th address: 0xffff0550 default value: 0x0000 access: read/write function: this 16-bit mmr sets the threshold against which the absolute value of the i-adc conversion result is compared. in unipolar mode, adc0th[15:0] are compared, and in twos complement mode, adc0th[14:0] are compared. current channel adc threshold count limit register name: adc0tcl address: 0xffff0554 default value: 0x01 access: read/write function: this 8-bit mmr determines how many cumulative (that is, values that are below the threshold decrement or that reset the count to 0) i-adc conversion result readings above adc0th must occur before the i-adc comparator threshold bit is set in the adcsta mmr, generating an adc interrupt. the i-adc comparator threshold bit is asserted as soon as adc0thv = adc0tcl. current channel adc threshold count register name: adc0thv address: 0xffff0558 default value: 0x00 access: read only function: this 8-bit mmr is incremented every time the absolute value of an i-adc conversion result is |i| adc0th. this register is decremented or reset to 0 every time the absolute value of an i-adc conversion result is |i| < adc0th. the configuration of this function is enabled via the current channel adc comparator bits in the adccfg mmr.
aduc7036 rev. b | page 54 of 132 current channel adc accumulator register name: adc0acc address: 0xffff055c default value: 0x00000000 access: read only function: this 32-bit mmr holds the current accumulator value. the i-adc ready bit in the adcsta mmr should be used to determine when it is safe to read this mmr. the mmr value is reset to 0 by disabling the accumulator in the adccfg mmr or reconfiguring the current channel adc. low power voltage reference scaling factor register name: adcref address: 0xffff057c default value: part specific, factory programmed access: read/write. care should be taken not to write to this register. function: this mmr allows user code to correct for the initial error of the lpm reference. value 0x8000 corresponds to no error when compared to the normal mode reference. the magni- tude of the adc result should be multiplied by the value in adcref and divided by 0x8000 to compensate for the actual value of the low power reference. if the lpm voltage reference is 1% below 1.2 v, the value of adcref is approximately 0x7eb9. if the lpm voltage reference is 1% above 1.2 v, the value of adcref is approximately 0x8147. this register corrects the effective value of the lpm reference at the temperature at which the reference is measured during the analog devices, inc., production flow, which is 25c. there is no change to the temperature coefficient of the lpm reference when using the adcref mmr. this register should not be used if the precision reference is being used in low power mode (if adcmde[5] is set). adc power modes of operation the adcs can be configured into various reduced or full power modes of operation by changing the configuration of adcmde[4:3], and the arm7 mcu can be configured in low power modes of operation (powcon[5:3]). the core power modes are independently controlled and are not related to the adc power modes described in the following sections. adc normal power mode in normal mode, the current and voltage/temperature channels are fully enabled. the adc modulator clock is 512 khz and enables the adcs to provide regular conversion results at a rate between 4 hz and 8 khz (see the adc filter register section). both channels are under full control of the mcu and can be reconfigured at any time. the default adc update rate for all channels in this mode is 1 khz. note that the i-adc and v-/t-adc channels can be configured to initiate periodic single conversion cycles in normal power mode with high accuracy before returning to adc full power-down mode. this flexibility is facilitated by full mcu control via the adcmde mmr, which ensures the feasibility of continuous periodic monitoring of battery current, voltage, and temperature settings while minimizing the average dc current consumption. in adc normal mode, the pll must not be powered down. adc low power mode in adc low power mode, the i-adc is enabled in a reduced power and reduced accuracy configuration. the adc modu- lator clock is driven directly from the on-chip 131 khz low power oscillator, which allows the adc to be configured at update rates as low as 1 hz (adcflt). the gain of the adc in this mode is fixed at 128. all adc peripheral functions (result counter, digital comparator and accumulator) described in the adc normal power mode section can also be enabled in low power mode. typically, in low power mode, only the i-adc is configured to run at a low update rate, continuously monitoring battery current. the mcu is in power-down mode and wakes up when the i-adc interrupts the mcu. such an interrupt occurs after the i-adc detects a current conversion beyond a preprogrammed threshold, a setpoint, or a set number of conversions. it is also possible to select either the adc precision voltage reference or the adc low power mode voltage reference via adcmde[5]. adc low power plus mode in low power plus mode, the i-adc channel is enabled in a mode almost identical to low power mode (adcmde[4:3]). however, in this mode, the i-adc gain is fixed at 512, and the adc consumes an additional 200 a (approximately) to yield improved noise performance relative to the low power mode setting. all adc peripheral functions (result counter, digital comparator, and accumulator) described in the adc normal power mode section can also be enabled in low power plus mode. as in low power mode, only the i-adc is configured to run at a low update rate, continuously monitoring battery current. the mcu is in power-down mode and wakes up only when the i-adc interrupts the mcu. this happens after the i-adc detects a current conversion result that exceeds a preprogrammed threshold or a setpoint. it is also possible to select either the adc precision voltage reference or the adc low power mode voltage reference via adcmde[5].
aduc7036 rev. b | page 55 of 132 ?100 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 attenuation (db) frequency (khz) adc comparator and accumulator the incorporation of comparator logic on the i-adc allows the i-adc result to generate an interrupt after a predefined number of conversions has elapsed or a programmable threshold value has been exceeded. every i-adc result can be compared with a preset threshold level (adc0th) that is set via adccfg[4:3]. in this case, an mcu interrupt is generated if the absolute (sign independent) value of the adc result is greater than the preprogrammed comparator threshold level. alternatively, as an extended function of the comparator, user code can configure a threshold counter (adc0thv) to monitor the number of i-adc results that have occurred above or below the preset threshold level. in this case, an adc interrupt is generated when the threshold counter reaches a preset value that is set via adc0tcl. 07474-021 by also incorporating a 32-bit accumulator (adc0acc) function that can be configured via adccfg[6:5], the i-adc can add or subtract multiple i-adc sample results. user code can read the accumulated value directly (adc0acc) without any further software processing. adc sinc3 digital filter response the overall frequency response on all aduc7036 adcs is dominated by the low-pass filter response of the on-chip sinc3 digital filters. the sinc3 filters are used to decimate the adc - modulator output data bit stream to generate a valid 16-bit data result. the digital filter response is identical for all adcs and is configured via the 16-bit adc filter register (adcflt). this register determines the overall throughput rate of the adcs. the noise resolution of the adcs is determined by the pro- grammed adc throughput rate. in the case of the current channel adc, the noise resolution is determined by throughput rate and selected gain. the overall frequency response and the adc throughput is dominated by the configuration of the sinc3 filter decimation factor (sf) bits (adcflt[6:0]) and the averaging factor (af) bits (adcflt[13:8]). due to limitations on the digital filter internal data path, there are some limitations on the allowable combinations of sf and af that can be used to generate a required adc output rate. this restriction limits the minimum adc update to 4 hz in normal power mode and to 1 hz in low power mode. the calculation of the adc throughput rate is detailed in the adcflt bit designations table (see table 39 ), and the restrictions on allowable combinations of af and sf values are outlined in tabl e 41 . by default, setting adcflt = 0x0007 configures the adcs for a throughput of 1 khz with all other filtering options (chop, running average, averaging factor, and sinc3 modify) disabled. a typical filter response based on this default configuration is shown in figure 21 . figure 21. typical digital filter response at f adc = 1 khz (adcflt = 0x0007) in addition, a sinc3 modify bit (adcflt[7]) is available in the adcflt register. this bit is set by user code and modifies the standard sinc3 frequency response to increase the filter stop- band rejection by approximately 5 db. this is achieved by inserting a second notch at the location determined by f notch2 = 1.333 f notch where f notch is the location of the first notch in the response. there is a slight increase in adc noise if the sinc3 modify bit is active. figure 22 shows the modified 1 khz filter response when the sinc3 modify bit is active. the new notch is clearly visible at 1.33 khz, as is the improvement in stop-band rejection when compared with the standard 1 khz response. attenuation (db) frequency (khz) ?100 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0 0.5 1.5 2.5 3.5 4.0 4.5 3.0 2.0 1.0 5.0 07474-022 figure 22. modified sinc3 di gital filter response at f adc = 1 khz (adcflt = 0x0087)
aduc7036 rev. b | page 56 of 132 ?100 ?90 024681012141618202224 frequency (khz) in adc normal power mode, the maximum adc throughput rate is 8 khz. this is configured by setting the sf and af bits in the adcflt mmr to 0, with all other filtering options disabled. as a result, 0x0000 is written to adcflt. figure 23 shows a typical 8 khz filter response based on these settings. 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 attenuation (db) 07474-023 ?100 ?90 024681012141618202224 frequency (khz) figure 23. typical digital filter response at f adc = 8 khz (adcflt = 0x0000) a modified version of the 8 khz filter response can be configured by setting the running average bit (adcflt[14]). as a result, an additional running-average-by-two filter is introduced on all adc output samples, which further reduces the adc output noise. in addition, by maintaining an 8 khz adc throughput rate, the adc settling time is increased by one full conversion period. the modified frequency response for this configuration is shown in figure 24 . 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 attenuation (db) 07474-024 ?100 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 02 0 0 180160140120100 8060 4020 attenuation (db) frequency (khz) figure 24. typical digital filter response at f adc = 8 khz (adcflt = 0x4000) at very low throughput rates, the chop enable bit in the adcflt register can be enabled to minimize offset errors and, more importantly, temperature drift in the adc offset error. with chop enabled, there are two primary variables (sinc3 decimation factor and averaging factor) available to allow the user to select an optimum filter response, but there is a trade-off between filter bandwidth and adc noise. for example, with the chop enable bit (adcflt[15]) set to 1, the sf value (adcflt[6:0]) increa ses to 0x1f (31 decimal) and an af value (adcflt[13:8]) of 0x16 (22 decimal) is selected, resulting in an adc throughput of 10 hz. the frequency response in this case is shown in figure 25 . 07474-025 ?100 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 06 0 40 20 attenuation (db) frequency (khz) figure 25. typical digital filter response at f adc = 10 hz (adcflt = 0x961f) changing sf to 0x1d and setting af to 0x3f with the chop enable bit still enabled configures the adc with its minimum throughput rate of 4 hz in normal mode. the digital filter frequency response with this configuration is shown in figure 26 . 07474-026 figure 26. typical digital filter response at f adc = 4 hz (adcflt = 0xbf1d) in adc low power mode, the - modulator clock of the adc is no longer driven at 512 khz, but is driven directly from the on-chip, low power, 131 khz oscillator. subsequently, if normal mode is used for the same adcflt configuration, all filter values should be scaled by a factor of approximately 4. therefore, it is possible to configure the adc for 1 hz throughput in low power mode. the filter frequency response for this configuration is shown in figure 27 .
aduc7036 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 attenuation (db) rev. b | page 57 of 132 ?100 ?90 02 0 1816141210 8642 frequency (khz) in general, it is possible to program different values of sf and af in the adcflt register and achieve the same adc update rate. however, in practical terms, users should consider the trade- off between frequency response and adc noise for any value of adcflt. for optimum filter response and adc noise when using combinations of sf and af, best practice suggests choosing an sf in the range of 16 decimal to 40 decimal, or 0x10 to 0x28, and then increasing the af value to achieve the required adc throughput. table 43 provides information about some common adcflt configurations. 07474-027 figure 27. typical digital filter response at f adc = 1 hz (adcflt = 0xbd1f) table 43. common adcflt configurations adc mode sf af other configuration adcflt f adc t settle normal 0x1d 0x3f chop on 0xbf1d 4 hz 0.5 sec normal 0x1f 0x16 chop on 0x961f 10 hz 0.2 sec normal 0x07 0x00 none 0x0007 1 khz 3 ms normal 0x07 0x00 sinc3 modify 0x0087 1 khz 3 ms normal 0x03 0x00 running average 0x4003 2 khz 2 ms normal 0x00 0x00 running average 0x4000 8 khz 0.5 ms low power 0x10 0x03 chop on 0x8310 20 hz 100 ms low power 0x10 0x09 chop on 0x8910 10 hz 200 ms low power 0x1f 0x3d chop on 0xbd1f 1 hz 2 sec
aduc7036 rev. b | page 58 of 132 adc calibration a s shown in detail in the top-level diagrams ( figure 17 and figure 18 ), the signal flow through all adc channels can be described as follows: 1. an input voltage is applied through an input buffer (and through pga in the case of the i-adc) to the - modulator. 2. the modulator output is applied to a programmable digital decimation filter. 3. the filter output result is then averaged if chopping is used. 4. an offset value (adcxof) is subtracted from the result. 5. this result is scaled by a gain value (adcxgn). 6. the result is formatted as twos complement/offset binary and rounded to 16 bits or clamped to full scale. each adc has a specific offset and gain correction or calibra- tion coefficient associated with it that are stored in mmr-based offset and gain registers (adcxof and adcxgn). the offset and gain registers can be used to remove offsets and gain errors within the part, as well as system-level offset and gain errors external to the part. these registers are configured at power-on with a factory- programmed calibration value. these factory-set calibration values vary from part to part, reflecting the manufacturing variability of internal adc circuits. however, these registers can also be overwritten by user code if the adc is in idle mode and are automatically overwritten if an offset or gain calibration cycle is initiated by the user through the adc operation mode configuration bits in the adcmde[2:0] mmr. two types of automatic calibration are available to the user: self-calibration or system calibration. self-calibration in self-calibration of offset errors, the adc generates its calibration coefficient based on an internally generated 0 v, whereas in self-calibration of gain errors, the coefficient is based on the full-scale voltage. although self-calibration can correct offset and gain errors within the adc, it cannot compensate for external errors in the system, such as shunt resistor tolerance/drift and external offset voltages. note that in self-calibration mode, adc0gn must contain the values for pga = 1 before a calibration scheme is started. system calibration in system calibration of offset errors, the adc generates its calibration coefficient based on an externally generated zero- scale voltage, whereas in system calibration of gain errors, the coefficient is based on the full-scale voltage. the calibration coefficient is applied to the external adc input for the duration of the calibration cycle. the duration of an offset calibration is a single conversion cycle (3/f adc chop off, 2/f adc chop on) before returning the adc to idle mode. a gain calibration is a two-stage process and, there- fore, takes twice as long as an offset calibration cycle. when a calibration cycle is initiated, any ongoing adc conversion is immediately halted, the calibration is automatically performed at the adc update rate programmed in adcflt, and the adc is always returned to idle after any calibration cycle. it is strongly recommended that adc calibration be initiated at as low an adc update rate as possible (and, therefore, requires a high sf value in adcflt) to minimize the impact of adc noise during calibration. using the offset and gain calibration if the chop enable bit, adcflt[15], is enabled, internal adc offset errors are minimized and an offset calibration may not be required. if chopping is disabled, however, an initial offset calibration is required and may need to be repeated, particularly after a large change in temperature. depending on system accuracy requirements, a gain calibration, particularly in the context of the i-adc (with internal pga), may need to be performed at all relevant system gain ranges. if it is not possible to apply an external full-scale current on all gain ranges, apply a lower current and then scale the result produced by the calibration. for example, apply a 50% current, and then divide the resulting adc0gn value by 2 and write this value back into adc0gn. note that there is a lower limit for the input signal that can be applied during a system calibration because adc0gn is only a 16-bit register. the input span (that is, the difference between the system zero-scale value and the system full-scale value) should be greater than 40% of the nominal full- scale-input range (that is, >40% of vref/gain). the on-chip flash/ee memory can be used to store multiple calibration coefficients. these calibration coefficients can be copied directly into the relevant calibration registers by user code and are based on the system configuration. in general, the simplest way to use the calibration registers is to let the adc calculate the values required as part of the adc automatic calibration modes. a factory-programmed or end-of-line calibration for the i-adc is a two-step procedure. 1. apply 0 a current. configure the adc in the required pga setting, and write to adcmde[2:0] to perform a system zero-scale calibration. this writes a new offset calibration value into adc0of. 2. apply a full-scale current for the selected pga setting. write to adcmde to perform a system full-scale calibration. this writes a new gain calibration value into adc0gn. understanding the offset and gain calibration registers the output of a typical block in the adc signal flow (described in the adc sinc3 digital filter response section through the using the offset and gain calibration section) can be consid- ered a fractional number with a span for a full-scale input of approximately 0.75. the span is less than 1 because there is attenuation in the modulator to accommodate some overrange capacity on the input signal. the exact value of the attenuation varies slightly from part to part because of manufacturing tolerances.
aduc7036 rev. b | page 59 of 132 for the current channel adc, the offset coefficient is read from the adc0of calibration register and is a 16-bit, twos complement number. the range of this number, in terms of the signal chain, is effectively 1. therefore, 1 lsb of the adc0of register is not the same as 1 lsb of the adc0dat register. a positive value of adc0of indicates that when offset is subtracted from the output of the filter, a negative value is added. the nominal value of this register is 0x0000, indicating zero offset is to be removed. the actual offset of the adc can vary slightly from part to part and at different pga gains. the offset within the adc is minimized if the chopping mode is enabled (that is, adcflt[15] = 1). the gain coefficient is read from the adc0gn register and is a unitless scaling factor. the 16-bit value in this register is divided by 16,384 and then multiplied by the offset-corrected value. the nominal value of this register equals 0x5555, corresponding to a multiplication factor of 1.3333, and scales the nominal 0.75 signal to produce a full-scale output signal of 1. the resulting output signal is checked for overflow/underflow and converted to twos complement or unipolar mode before being output to the data register. the actual gain and the required scaling coefficient for zero gain error vary slightly from part to part at different pga set- tings in normal and low power modes. the value downloaded into adc0gn during a power-on reset represents the scaling factor for a pga gain of 1. if a different pga setting is used, however, some gain error may be present. to correct this error, overwrite the calibration coefficients via user code or perform an adc calibration. the simplified adc transfer function can be described as nom ref in out adcxgn adcxgn adcxof v pgav adc ? ? ? ? ? ? ? = where the equation is valid for the voltage/temperature chan- nel adc. nom ref in out adcxgn adcxgn adcxof k v pgav adc ? = ? ? ? ? ? ? where k is dependent on the pga gain setting and adc mode. normal mode in normal mode, k = 1 for pga gains of 1, 4, 8, 16, 32, and 64; k = 2 for pga gains of 2 and 128; k = 4 for a pga gain of 256; and k = 8 for a pga gain of 512. low power mode in low power mode, k = 32 for a pga gain of 128. in addition, if the reg_avdd/2 reference is used, the k factor doubles. low power plus mode in low power plus mode, k = 8 for a pga gain of 512. in addition, if the reg_avdd/2 reference is used, the k factor doubles. adc diagnostics the aduc7036 features a diagnostic capability and open- circuit detection on both adcs. current adc diagnostics the aduc7036 features the capability to detect open-circuit conditions on the current channel inputs. this is accomplished using the two current sources on iin+ and iin?, which are controlled via adc0con[14:13]. note that the iin+ and iin? current sources have a tolerance of 30%. therefore, a pga gain 2 (adc0con[3:0] 0001) must be used when current sources are enabled. temperature adc diagnostics the aduc7036 features the capability to detect open-circuit conditions on the temperature channel inputs. this is accomplished using the two current sources on vtemp and gnd_sw, which are controlled via adc1con[14:13]. voltage adc diagnostics the aduc7036 features the capability to detect open-circuit conditions on the voltage channel input. this is accomplished using the current source on the voltage attenuator, controlled by the high voltage register hvcfg1[7].
aduc7036 rev. b | page 60 of 132 power supply support circuits the aduc7036 incorporates two on-chip low dropout (ldo) regulators that are driven directly from the battery voltage to generate a 2.6 v internal supply. this 2.6 v supply is then used as the supply voltage for the arm7 mcu and the peripherals, including the on-chip precision analog circuits. the digital ldo functions with two output capacitors (2.2 f and 0.1 f) in parallel on reg_dvdd, whereas the analog ldo functions with an output capacitor (0.47 f) on reg_avdd. the esr of the output capacitor affects stability of the ldo control loop. an esr of 5 or less for frequencies greater than 32 khz is recommended to ensure the stability of the regulators. in addition, the power-on reset (por), power supply monitor (psm), and low voltage flag (lvf) functions are integrated to ensure safe operation of the mcu, as well as continuous monitoring of the battery power supply. the por circuit is designed to operate with a vdd (0 v to 12 v) power-on time of greater than 100 s. it is, therefore, recom- mended that the external power supply decoupling components be carefully selected to ensure that the vdd supply power-on time can always be guaranteed to be greater than 100 s, regardless of the vbat power-on conditions. the series resistor and decoupling capacitor combination on vdd should be chosen to result in an rc time constant of at least 100 s (for example, 10 and 10 f, as shown on figure 59 ). as shown in figure 28 , when the supply voltage on vdd reaches a typical operating voltage of 3 v, a por signal keeps the arm core in reset state for 20 ms. this ensures that the regulated power supply voltage (reg_dvdd) applied to the arm core and associated peripherals is greater than the minimum oper- ational voltage, thereby guaranteeing full functionality. a por flag is set in the rststa mmr to indicate a por event has occurred. the aduc7036 also features a psm function. when enabled through hvcfg0[3], the psm continuously monitors the voltage at the vdd pin. if this voltage drops below 6 v typical, the psm flag is automatically asserted and can generate a system interrupt if the high voltage irq is enabled via irqen[16] or fiqen[16]. an example of this operation is shown in figure 28 . at voltages below the por level, an additional low voltage flag can be enabled (hvcfg0[2]). this flag can be used to indicate that the contents of the sram remain valid after a reset event. the operation of the low voltage flag is shown in figure 28 . when hvcfg0[2] is enabled, the status of this bit can be monitored via hvmon[3]. if the hvcfg0[2] bit is set, the sram contents are valid. if this bit is cleared, the sram contents may become corrupted. vdd 12 v 3v typ 2.6v 20ms typ psm trip 6v typ por trip 3v typ lvf trip 2.1v typ reg_dvdd por_trip reset_core (internal signal) enable_psm enable_lvf 07474-028 figure 28. typical power-on cycle
aduc7036 rev. b | page 61 of 132 system clocks the aduc7036 integrates a very flexible clocking system that allows clock generation from one of three sources: an integrated on-chip precision oscillator, an integrated on-chip low power oscillator, or an external watch crystal. these three options are shown in figure 29 . each of the internal oscillators is divided by 4 to generate a clock frequency of 32.768 khz. the pll locks onto a multiple (625) of 32.768 khz, supplied by either of the internal oscillators or the external crystal to provide a stable 20.48 mhz clock for the system. the core can operate at this frequency or at a binary submultiple of this frequency, thereby allowing power saving when peak performance is not required. by default, the pll is driven by the low power oscillator that generates a 20.48 mhz clock source. the arm7tdmi core, in turn, is driven by a clock divider (set by the cd bits in the powcon register). by default, the cd bits are configured to divide the pll output by 2, thereby generating a core clock of 10.24 mhz. the divide factor can be modified to generate a binary-weighted divider factor in the range of 1 to 128 that can be altered dynamically by user code. the adc is driven by the output of the pll, which is divided to provide an adc clock source of 512 khz. in low power mode, the adc clock source is switched from the standard 512 khz to the low power 131 khz oscillator. note that the low power oscillator drives both the watchdog and core wake-up timers through a divide-by-4 circuit. a detailed block diagram of the aduc7036 clocking system is shown in figure 29 . spi core clock pll output (20.48mhz) uart core clock precision 131khz div 4 precision oscillator low power oscillator external 32.768khz low power 131khz div 4 pllcon pll flash controller eclk 2.5mhz precision 32.768khz low power 32.768khz pll output 20.48mhz crystal circuitry external crystal (optional) pll lock 1 8 adcmde clock divider core clock 1 2 cd mcu adc clock adc high accurcy calibration counter external 32.768khz precision 131khz low power calibration counter low power oscillator timer0 lifetime core clock external 32.768khz precision 32.768khz low power 32.768khz gpio_5 timer1 l-purpose genera core clock gpio_8 low power 32.768khz timer2 ke-up wa core clock low power 32.768khz precision 32.768khz external 32.768khz wa tchdog timer3 low power 32.768khz timer4 sti low power 32.768khz core clock l synchr in h/w onization low power 32.768khz pll output (5mhz) 0 7474-029 figure 29. system clock generation
aduc7036 rev. b | page 62 of 132 the operating mode, clocking mode, and programmable clock divider are controlled using two mmrs, pllcon and powcon, and the status of the pll is indicated by pllsta. pllcon controls the operating mode of the clock system, and powcon controls both the core clock frequency and the power-down mode. pllsta indicates the presence of an oscillator on the xtal1 pin and provides information about the pll lock status and the pll interrupt. before powering down the aduc7036, it is recommended that the clock source for the pll be switched to the low power 131 khz oscillator to reduce wake-up time. the low power oscillator is always active. when the aduc7036 wakes up from power-down, the mcu core begins executing code as soon as the pll starts oscillating. this code execution occurs before the pll has locked to a fre- quency of 20.48 mhz. to ensure that the flash/ee memory controller is executing with a valid clock, the controller is driven with a pll output divide-by-8 clock source while the pll is locking. when the pll locks, the pll output is switched from the pll output divide-by-8 to the locked pll output. if user code requires an accurate pll output, user code must poll the pll lock status bit (pllsta[1]) after a wake-up before resuming normal code execution. the pll is locked within 2 ms if the pll is clocked from an active clock source, such as a low power 131 khz oscillator, after waking up. pllcon is a protected mmr with two 32-bit keys: pllkey0 (prewrite key) and pllkey1 (postwrite key). they key values are as follows: pllkey0 = 0x000000aa pllkey1 = 0x00000055 powcon is a protected mmr with two 32-bit keys: powkey0 (prewrite key) and powkey1 (postwrite key). powkey0 = 0x00000001 powkey1 = 0x000000f4 an example of writing to both mmrs is as follows: powkey0 = 0x01 //powcon key powcon = 0x00 //full power-down powkey1 = 0xf4 //powcon key ia1*ia2 //dummy cycle to clear the pipeline, where ia1 and ia2 are defined as longs and are not 0 pllkey0 = 0xaa //pllcon key pllcon = 0x0 //switch to low power osc. pllkey1 = 0x55 //pllcon key ia1*ia2 //dummy cycle to prevent flash/ee access during clock change system clock registers pllsta register name: pllsta address: 0xffff0400 default value: n/a access: read only function: this 8-bit register allows user code to monitor the lock state of the pll and the status of the external crystal. table 44. pllsta mmr bit designations bit description 7 to 3 reserved. 2 xtal clock. this read only bit is a live representation of the current logic level on xtal1. it indicates if an external clock source is present by alternating between high and low at a frequency of 32.768 khz. 1 pll lock status bit. this is a read only bit. set when the pll is locked and outputting 20.48 mhz. cleared when the pll is not locked and outputting an f core divide-by-8 clock source. 0 pll interrupt. set if the pll lock status bit signal goes low. cleared by writing 1 to this bit.
aduc7036 rev. b | page 63 of 132 pllcon prewrite key name: pllkey0 address: 0xffff0410 access: write only key: 0x000000aa function: this keyed register requires a 32-bit key value to be written before and after pllcon. pllkey0 is the prewrite key. pllcon postwrite key name: pllkey1 address: 0xffff0418 access: write only key: 0x00000055 function: this keyed register requires a 32-bit key value to be written before and after pllcon. pllkey1 is the postwrite key. pllcon register name: pllcon address: 0xffff0414 default value: 0x00 access: read/write function: this 8-bit register allows user code to dynamically select the pll source clock from three different oscillator sources. table 45. pllcon mmr bit designations bit description 7 to 2 reserved. these bits should be written as 0 by user code. 1 to 0 pll clock source. 1 00 = lower power, 131 khz oscillator. 01 = precision 131 khz oscillator. 10 = external 32.768 khz crystal. 11 = reserved. 1 if the user code switches mcu clock sources, a dummy mcu cycle should be included after the clock switch is written to pllcon. powcon prewrite key name: powkey0 address: 0xffff0404 access: write only key: 0x00000001 function: this keyed register requires a 32-bit key value to be written before and after powcon. powkey0 is the prewrite key. powcon postwrite key name: powkey1 address: 0xffff040c access: write only key: 0x000000f4 function: this keyed register requires a 32-bit key value to be written before and after powcon. powkey1 is the post- write key.
aduc7036 rev. b | page 64 of 132 powcon register name: powcon address: 0xffff0408 default value: 0x79 access: read/write function: this 8-bit register allows user code to dynamically enter various low power modes and modify the cd divider that cont rols the speed of the arm7tdmi core. table 46. powcon mmr bit designations bit description 7 precision 131 khz input enable. set by the user to enable the precision 131 khz input enable. th e precision 131 khz oscillator mu st also be enabled using hvcf g0[6]. setting this bit increases current consumption by approxim ately 50 a. it should be disabled when not in use. cleared by the user to power-down the precision 131 khz input enable. 6 xtal power-down. set by the user to enable th e external crystal circuitry. cleared by the user to power down the external crystal circuitry. 5 pll power-down. timer peripherals power down if driven from the pll output clock. timers driven from an active clock source remain in normal power mode. set by default and set by hardware on a wake-up event. cleared to 0 to power down the pll. the pll cannot be powered down if either the core or peripherals are enabled: bit 3, bit 4, and bit 5 must be cleared simultaneously. 4 peripherals power-down. the peripherals that are powered down by this bit are as follows: sram, flash/ee memory and gpio interfaces, and spi and uart serial ports. set by default and/or by hardware on a wake-up event. the wake-up timer (timer2) can still be active if driven from a low powe r oscillator even if this bit is set. cleared to power down the peripherals. the peripherals cannot be powered down if the core is enabled: bit 3 and bit 4 must be cleared simultaneously. lin can still respond to wake-up events even if this bit is cleared. 3 core power-down. if user code powers down the mcu, include a dummy mcu cycle after the power-down command is written to powcon. set by default, and set by hardware on a wake-up event. cleared to power down the arm core. 2 to 0 cd core clock divider bits. 000 = 20.48 mhz, 48.83 ns. 001 = 10.24 mhz, 97.66 ns (this is default setting on power up). 010 = 5.12 mhz, 195.31 ns. 011 = 2.56 mhz, 390.63 ns. 100 = 1.28 mhz, 781.25 ns. 101 = 640 khz, 1.56 s. 110 = 320 khz, 3.125 s. 111 = 160 khz, 6.25 s.
aduc7036 rev. b | page 65 of 132 low power clock calibration the low power 131 khz oscillator can be calibrated using either the precision 131 khz oscillator or an external 32.768 khz watch crystal. two dedicated calibration counters and an oscillator trim register are used to implement this feature. the first counter (counter 0) is nine bits wide and is clocked by an accurate clock oscillator, either the precision oscillator or an external watch crystal. the second counter (counter 1) is 10 bits wide and is clocked by the low power oscillator, either directly at 131 khz or through a divide-by-4 block generating 32.768 khz. the source for each calibration counter should be of the same frequency. the trim register (osc0trm) is an 8-bit-wide register, the lower four bits of which are user-accessible trim bits. increasing the value in osc0trm decreases the frequency of the low power oscillator. conversely, decreasing the value in osc0trm increases the frequency. based on a nominal frequency of 131 khz, the typical trim range is between 127 khz and 135 khz. th e clock calibration mode is configured and controlled by the following mmrs: ? o sc0con: control bits for calibration. ? o sc0sta: calibration status register. ? o sc0val0: 9-bit counter, counter 0. ? o sc0val1: 10-bit counter, counter 1. ? osc0trm: oscillator trim register. a c alibration routine flowchart is shown in figure 30 . user code configures and enables the calibration sequence using osc0con. when the osc0val0 precision power oscillator calibration counter reaches 0x1ff, both counters are disabled. user code then reads back the value of the low power oscillator calibration counter. there are three possible scenarios: ? osc0val0 = osc0val1. no further action is required. ? osc0val0 > osc0val1. the low power oscillator is running slow. osc0trm must be decreased. ? osc0val0 < osc0val1. the low power oscillator is running fast. osc0trm must be increased. when the value in osc0trm has been changed, the routine should be run again, and the new frequency should be checked. using the internal precision 131 khz oscillator requires approx- imately 4 ms to execute the calibration routine. if the external 32.768 khz crystal is used, the time increases to 16 ms. prior to the start of the clock calibration routine, the user must switch to either the precision 131 khz oscillator or the external 32.768 khz watch crystal to serve as the pll clock source. if this is not done, the pll may lose lock each time osc0trm is modified, thereby increasing the time required to calibrate the low power oscillator. begin calibration routine while osc0sta[0] = 1 increase osc0trm decrease osc0trm osc0val0 < osc0val1 osc0val0 > osc0val1 is error within desired level? end calibration routine osc0val0 = osc0val1 no yes 07474-030 figure 30. osc0trm calibration routine
aduc7036 rev. b | page 66 of 132 osc0trm register name: osc0trm address: 0xffff042c default value: 0xx8 access: read/write function: this 8-bit register controls the low power oscillator trim. table 47. osc0trm mmr bit designations bit description 7 to 4 reserved. should be written as 0. 3 to 0 user trim bits. osc0con register name: osc0con address: 0xffff0440 default value: 0x00 access: read/write function: this 8-bit register controls the low power oscillator calibration routine. table 48. osc0con mmr bit designations bit description 7 to 5 reserved. should be written as 0. 4 calibration source. set to select external 32.768 khz crystal. cleared to select internal precision 131 khz oscillator. 3 calibration reset. set to reset the calibratio n counters and disable the calibration logic. 2 set to clear osc0val1. 1 set to clear osc0val0. 0 calibration enable. set to begin calibration. cleared to abort calibration. osc0sta register name: osc0sta address: 0xffff0444 default value: 0x00 access: read only function: this 8-bit register gives the status of the low power oscillator calibration routine. table 49. osc0sta mmr bit designations bit description 7 to 2 reserved. 1 calibration complete. set by hardware on full completion of a calibration cycle. cleared by a read of osc0val1. 0 set if calibration is in progress. cleared if calibration is complete. osc0val0 register name: osc0val0 address: 0xffff0448 default value: 0x0000 access: read only function: this 9-bit counter is clocked from either the 131 khz precision oscillator or the 32.768 khz external crystal. osc0val1 register name: osc0val1 address: 0xffff044c default value: 0x0000 access: read only function: this 10-bit counter is clocked from the low power, 131 khz oscillator.
aduc7036 rev. b | page 67 of 132 processor reference peripherals interrupt system there are 16 interrupt sources on the aduc7036 that are con- trolled by the interrupt controller. most interrupts are generated from the on-chip peripherals, such as the adc and uart. the arm7tdmi cpu core recognizes interrupts as one of only two types: a normal interrupt request (irq) and a fast interrupt request (fiq). all the interrupts can be masked separately. the control and configuration of the interrupt system is managed through nine interrupt-related registers, with four dedicated to irq and four dedicated to fiq. an additional mmr is used to select the programmed interrupt source. the bits in each irq and fiq register represent the same interrupt source as described in table 50 . irqsta/fiqsta should be saved immediately upon entering the interrupt service routine (isr) to ensure that all valid interrupt sources are serviced. the interrupt generation route through the arm7tdmi core is shown in figure 31 . consider an example in which timer0 is configured to generate a timeout every 1 ms. after the first 1 ms timeout, fiqsig[2] or irqsig[2] is set and can be cleared only by writing to t0clri. if timer0 is not enabled in either irqen or fiqen, then fiqsta/ irqsta[2] is not set and an interrupt does not occur. however, if timer0 is enabled in either irqen or fiqen, then either fiqsta[2] or irqsta[2] is set or an interrupt (fiq or irq) occurs. note that the irq and fiq bit definitions in the cpsr control interrupt recognition only by the arm core and not by the peri- pherals. for example, if timer2 is configured to generate an irq via irqen, the irq interrupt bit is set (disabled) in the cpsr and the aduc7036 is powered down. when an interrupt occurs, the peripherals wake up, but the arm core remains powered down. this is equivalent to powcon = 0x71. the arm core can then be powered up only by a reset event. table 50. irq/fiq mmrs bit designations bit description comments 0 all interrupts ored (fiq only) 1 swi: not used in irqen/irqclr and fiqen/fiqclr 2 timer0 see the timer0lifetime timer section. 3 timer1 see the timer1 section. 4 timer2 or wake-up timer see the timer2wake-up timer section. 5 timer3 or watchdog timer see the timer3watchdog timer section. 6 timer4 or sti timer see the timer4sti timer section. 7 lin hardware see the lin (local interconnect network) interface section. 8 flash/ee interrupt see the flash/ee control interface section. 9 pll lock see the system clocks section. 10 adc see the 16-bit, - analog-to-digital converters section. 11 uart see the uart serial interface section. 12 spi master see the serial peripheral interface section. 13 xirq0 (gpio irq0) see the general-purpose i/o section. 14 xirq1 (gpio irq1) see the general-purpose i/o section. 15 reserved 16 irq3 high voltage irq high voltage interrupt; see the high voltage peripheral control interface section. 17 spi slave see the serial peripheral interface section. 18 xirq4 (gpio irq4) see the general-purpose i/o section. 19 xirq5 (gpio irq5) see the general-purpose i/o section. 20 to 32 reserved reserved.
aduc7036 rev. b | page 68 of 132 normal interrupt (irq) request the irq request is the exception signal allowed to enter the processor in irq mode. it is used to service general-purpose interrupt handling of internal and external events. all 32 bits of the irqsta mmr are ored to create a single irq signal to the arm7tdmi core. the four 32-bit registers dedicated to irq are described in the irqsta register to the irqclr register sections. irqsta register name: irqsta adress: 0xffff0000 default value: 0x00000000 access: read only function: this register provides the status of the irq source that is currently enabled by irq source status (see figure 31 ). when a bit in this register is set to 1, the corresponding source generates an active irq request to the arm7tdmi core. there is no priority encoder or interrupt vector generation. this function is implemented in software in a common interrupt handler routine. irqsig register name: irqsig address: 0xffff0004 default value: 0x00000000 access: read only function: this 32-bit register reflects the status of the different irq sources. if a peripheral generates an irq signal, the corres- ponding bit in the irqsig is set; otherwise, the corresponding bit is cleared. the irqsig bits are cleared when the interrupt in the particular peripheral is cleared. all irq sources can be masked in the irqen mmr. irqsig is read only. irqen register name: irqen address: 0xffff0008 default value: 0x00000000 access: read/write function: this register provides the value of the current enable mask. when a bit in this register is set to 1, the corresponding source request is enabled to create an irq exception signal. when a bit is set to 0, the corresponding source request is disabled or masked and does not create an irq exception signal. the irqen register cannot be used to disable an interrupt. irqclr register name: irqclr address: 0xffff000c access: write only function: this register allows the irqen register to clear to mask an interrupt source. each bit set to 1 clears the corresponding bit in the irqen register without affecting the remaining bits. when used as a pair of registers, irqen and irqclr allow independent manipulation of the enable mask without requiring an automatic read-modify-write instruction. fast interrupt request (fiq) the fiq is the exception signal allowed to enter the processor in fiq mode. it is provided to service data transfer or communication channel tasks with low latency. the fiq interface is identical to the irq interface and provides the second-level interrupt (highest priority). four 32-bit registers are dedicated to fiq: fiqsig, fiqen, fiqclr, and fiqsta. all 32 bits of the fiqsta mmr are ored to create the fiq signal to the core and to bit 0 of both the fiq and irq registers (fiq source). the logic for fiqen and fiqclr does not allow an interrupt source to be enabled in both irq and fiq masks. as a side effect, a bit set to 1 in fiqen clears the same bit in irqen. likewise, a bit set to 1 in irqen clears the same bit in fiqen. an interrupt source can be disabled in both irqen and fiqen masks. programmed interrupts because the programmed interrupts are not maskable, they are controlled by another register, swicfg, that writes into both irqsta and irqsig registers and/or the fiqsta and fiqsig registers at the same time. the 32-bit register dedicated to software interrupt is swicfg; it is described in table 51 . this mmr allows the control of a pro- grammed source interrupt. table 51. swicfg mmr bit designations bit description 31 to 3 reserved. 2 programmed interrupt fiq. setting/clearing this bit corresponds to setting/clearing bit 1 of fiqsta and fiqsig. 1 programmed interrupt irq. setting/clearing this bit corr esponds to setting/clearing bit 1 of irqsta and irqsig. 0 reserved. note that any interrupt signal must be active for at least the minimum interrupt latency time to be detected by the interrupt controller and by the user in the irqsta or fiqsta register.
aduc7036 rev. b | page 69 of 132 irqsta fiqsta irqsig fiqsig timer0 timer1 timer2 timer3 lin h/w flash/ee pll lock adc uart spi xirqx irq fiq 07474-031 ir fi qen qen timer0 timer1 timer2 timer3 timer4 lin h/w flash/ee pll lock adc uart spi xirqx figure 31. interrupt structure
aduc7036 rev. b | page 70 of 132 timers t he aduc7036 features five general-purpose timer/counters. ? timer0, or the lifetime timer ? timer1, or general-purpose timer ? timer2, or the wake-up timer ? timer3, or the watchdog timer ? timer4, or the sti timer the five timers in their normal mode of operation can be in either free running mode or periodic mode. timers are started by writing data to the control register of the corresponding timer (txcon). the counting mode and speed depend on the configuration chosen in txcon. in normal mode, an irq is generated each time the value of the counter reaches 0 when counting down, or each time the counter value reaches full scale when counting up. an irq can be cleared by writing any value to clear the register of that particular timer (txclri). the three timers in their normal mode of operation can be either free-running or periodic. in free-running mode, starting with the value in the txld register, the counter decrements/increments from the maximum/ minimum value until zero/full scale and starts again at the maximum/minimum value. this means that, in free-running mode, txval is not reloaded when the relevant interrupt bit is set but the count simply rolls over as the counter underflows or overflows. in periodic mode, the counter decrements/increments from the value in the load register (txld mmr) until zero/full scale starts again from this value. this means when the relevant interrupt bit is set, txval is reloaded with txld and counting starts again from this value. loading the txld register with zero is not recommended. the value of a counter can be read at any time by accessing its value register (txval). in addition, timer0, timer1, and timer4 each have a capture register (t0cap, t1cap, and t4cap, respectively) that can hold the value captured by an enabled irq event. the irq events are described in table 52 . table 52. timer event capture bit description 0 timer0, or the lifetime timer 1 timer1, or general-purpose timer 2 timer2, or the wake-up timer 3 timer3, or the watchdog timer 4 timer4, or the sti timer 5 lin hardware 6 flash/ee interrupt 7 pll lock 8 adc 9 uart 10 spi master 11 xirq0 (gpio_0) 12 xirq1 (gpio_5) 13 reserved 14 irq3 high voltage interrupt 15 spi slave 16 xirq4 (gpio_7); see the general-purpose i/o section 17 xirq5 (gpio_8); see the general-purpose i/o section synchronization of timers across asynchronous clock domains the block diagram in figure 32 shows the interface between user timer mmrs and the core timer blocks. user code can access all timer mmrs directly, including txld, txval, txcon, and txclri. data must then transfer from these mmrs to the core timers (t0, t1, t2, t3, and t4) within the timer subsystem. theses core timers are buffered from the user mmr interface by the synchronization (sync) block. the principal of the sync block is to provide a method that ensures that data and other required control signals can cross asynchronous clock domains correctly. an example of asyn- chronous clock domains is the mcu running on the 10 mhz core clock, and timer2 running on the low power oscillator of 32 khz.
aduc7036 rev. b | page 71 of 132 t0 sync t1 sync t2 sync t3 sync t4 sync t0 t1 t2 t3 t4 t0irq t1irq t2irq t3irq wdrst t4irq t0 reg user mmr interface t1 reg t2 reg t3 reg t4 reg arm7tdmi amba core clock low power oscillator gpio high precision oscillator xtal 0 1 2 4 amba timer block 07474-058 unsynchronized signal synchronized signal timer 2 low power clock domain synchronizer flip-flops core clock (f core ) domain target_clock figure 32. timer block diagram 07474-059 figure 33. synchronizer for signals crossing clock domains as shown in figure 32 , the mmr logic and core timer logic reside in separate and asynchronous clock domains. any data coming from the mmr core clock domain and being passed to the internal timer domain must be synchronized to the internal timer clock omain to ensure it is latched correctly into the core timer clock domain. this is achieved by using two flip-flops as shown in figure 33 to not only synchronize but also to double buffer the data and thereby ensuring data integrity in the timer clock domain. as a result of the synchronization block, while timer control data is latched almost immediately (with the fast, core clock) in the mmr clock domain, this data in turn will not reach the core timer logic for at least two periods of the selected internal timer domain clock. programming the timers understanding synchronization across timer domains also requires that the user code carefully programs the timers when stopping or starting them. the recommended code controls the timer block when stopping and starting the timers and when using different clock domains. this can critical, especially if timers are enabled to generate an irq or fiq exception; timer2 is used as an example. halting timer2 when halting timer2, it is recommended that the irqen bit for timer2 be masked (using irqclr). this prevents unwanted irqs from generating an interrupt in the mcu before the t2con control bits have been latched in the timer2 internal logic. irqclr = wakeup_timer_bit; //masking interrupts t2con=0x00; //halting the timer
aduc7036 rev. b | page 72 of 132 starting timer2 when starting timer2, it is recommended to first load timer2 with the required txld value. next, start the timer by setting the t2con bits as required. this enables the timer, but only once the t2con bits have been latched internally in the timer2 clock domain. therefore, it is advised that a delay of more than three clock periods (that is, 100 s for a 32 khz timer clock source) is inserted to allow both the t2ld value and the t2con value to be latched through the synchronization logic and reach the timer2 domain. after the delay, it is recommended that any (inadvertent) timer2 interrupts are now cleared using t2clri=0x00. finally, the timer2 system interrupt can be unmasked by setting the appro-priate bit in the irqen mmr. an example of this code is as follows, where the assumption is that timer2 is halted: example code t2ld = 0x1; //reload timer t2con = 0x02cf; //enable t2?low power osc, 32768 prescaler delay(100us); //include delay to ensure t2con bits take effect t2clri = 0 ; //*cleartimerirq irqen = wakeup_timer_bit; //unmask timer2
aduc7036 rev. b | page 73 of 132 timer0lifetime timer timer0 is a general-purpose, 48-bit up counter or a 16-bit up/down counter timer with a programmable prescaler. timer0 can be clocked from either the core clock or the low power 32.768 khz oscillator with a prescaler of 1, 16, 256, or 32,768. when the core is operating at 20.48 mhz with a prescaler of 1, a minimum reso- lution of 48.83 ns results. in 48-bit mode, timer0 counts up from 0. the current counter value can be read from t0val0 and t0val1. in 16-bit mode, timer0 can count up or down. a 16-bit value can be written to t0ld to load into the counter. the current counter value is read from t0val0. timer0 has a capture reg- ister (t0cap) that is triggered by a selected irq source initial assertion. when the capture register is triggered, the current timer value is copied to t0cap, and the timer continues running. this feature can be used to determine the assertion of an event with more accuracy than would be provided by servicing an interrupt alone. timer0 reloads the value from t0ld when timer0 overflows. the timer0 interface consists of six mmrs: t0ld, t0cap, t0val0, t0val1, t0clri, and t0con. t0ld is a 16-bit register holding the 16-bit value that is loaded into the counter. t0ld is available only in 16-bit mode. t0cap is a 16-bit register that holds the 16-bit value captured by an enabled irq event. t0cap is available only in 16-bit mode. t0val0 and t0val1 are 16-bit and 32-bit registers that hold the 16 lsbs and 32 msbs, respectively. t0val0 and t0val1 are read only registers. in 16-bit mode, 16-bit t0val0 is used. in 48-bit mode, both 16-bit t0val0 and 32-bit t0val1 are used. t0clri is an 8-bit register. writing any value to this register clears the interrupt. t0clri is available only in 16-bit mode. t0con is a configuration mmr and is described in table 53 . timer0 load register name: t0ld address: 0xffff0300 default value: 0x0000 access: read/write function: t0ld0 is the 16-bit register holding the 16-bit value that is loaded into the counter. this register is available only in 16-bit mode. timer0 clear register name: t0clri address: 0xffff0310 access: write only function: this 8-bit, write only mmr is written (with any value) by user code to clear the interrupt. timer0 value registers name: t0val0, t0val1 address: 0xffff0304, 0xffff0308 default value: 0x0000, 0x00000000 access: read only function: t0val0 and t0val1 are 16-bit and 32-bit registers that hold the 16 lsbs and 32 msbs, respectively. t0val0 and t0val1 are read only registers. in 16-bit mode, 16-bit t0val0 is used. in 48-bit mode, both 16-bit t0val0 and 32-bit t0val1 are used. timer0 capture register name: t0cap address: 0xffff0314 default value: 0x0000 access: read only function: this 16-bit register holds the 16-bit value captured by an enabled irq event. this register is available only in 16-bit mode. timer0 value low power 32.768khz oscillator precision 32.768khz oscillator external 32.768khz watch crystal core clock frequency prescaler 1, 16, 256, or 32,768 16-bit load 48-bit up counter 16-bit up/down counter timer0 irq capture irq[31:0] 07474-032 figure 34. timer0 block diagram
aduc7036 rev. b | page 74 of 132 timer0 control register name: t0con address: 0xffff030c default value: 0x00000000 access: read/write function: this 32-bit mmr configures the mode of operation for timer0. table 53. t0con mmr bit designations bit description 31 to 18 reserved. 17 event select bit. set by user to enable time capture of an event. cleared by user to disable time capture of an event. 16 to 12 event select range (0 to 17). the events are as defined in table 52 . 11 reserved. 10 to 9 clock select. 00 = core clock (default). 01 = low power 32.768 khz oscillator. 10 = external 32.768 khz watch crystal. 11 = precision 32.768 khz oscillator. 8 count up. available in 16-bit mode only. set by user for timer0 to count up. cleared by user for timer0 to count down (default). 7 timer0 enable bit. set by user to enable timer0. cleared by user to disable timer0 (default). 6 timer0 mode. set by user to operate in periodic mode. cleared by user to operate in free running mode (default). 5 reserved. 4 timer0 mode of operation. 0 = 16-bit operation (default). 1 = 48-bit operation. 3 to 0 prescaler. 0000 = source clock/1 (default). 0100 = source clock/16. 1000 = source clock/256. 1111 = source clock/32,768.
aduc7036 rev. b | page 75 of 132 timer1general-purpose timer timer1 is a general-purpose, 32-bit up/down counter with a programmable prescaler. the prescaler source can be the low power 32.768 khz oscillator, the core clock, or from one of two external gpios. this source can be scaled by a factor of 1, 16, 256, or 32,768. when the core is operating at 20.48 mhz and at cd = 0 with a prescaler of 1 (ignoring the external gpios), a min- imum resolution of 48.83 ns results. the counter can be formatted as a standard 32-bit value or as time expressed as hours:minutes:seconds:hundredths. timer1 has a capture register (t1cap) that is triggered by the initial assertion of a selected irq source. when the capture register is triggered, the current timer value is copied to t1cap, and the timer continues to run. this feature can be used to determine the assertion of an event with increased accuracy. the timer1 interface consists of five mmrs: t1ld, t1val, t1cap, t1clri, and t1con. t1ld, t1val, and t1cap are 32-bit registers that hold 32-bit unsigned integers. t1val and t1cap are read only. t1clri is an 8-bit register. writing any value to this register clears the timer1 interrupt. t1con is a configuration mmr and is described in table 54 . timer1 features a postscaler that allows the user to count the number of timer1 timeouts between 1 and 256. to activate the postscaler, the user sets bit 23 and writes the desired number to count into bits[24:31] of t1con. when that number of timeouts is reached, timer1 generates an interrupt if t1con[18] is set. note that if the part is in a low power mode and timer1 is clocked from the gpio or low power oscillator source, then timer1 continues to operate. timer1 reloads the value from t1ld when timer1 overflows. timer1 load register name: t1ld address: 0xffff0320 default value: after a reset, this register contains the upper half of the assembly lot id (0x00000000). access: read/write function: this 32-bit register holds the 32-bit value that is loaded into the counter. timer1 clear register name: t1clri address: 0xffff032c access: write only function: this 8-bit, write only mmr is written (with any value) by user code to clear the interrupt. timer1 value register name: t1val address: 0xffff0324 default value: 0xffffffff access: read only function: this 32-bit register holds the current value of timer1. timer1 value low power 3 2.768khz oscillator core clock frequency gpio gpio 32-bit load 32-bit up/down counter timer1 irq 8-bit postscaler capture irq[31:0] prescaler 1, 16, 256, or 32,768 07474-033 figure 35. timer1 block diagram
aduc7036 rev. b | page 76 of 132 timer1 capture register name: t1cap address: 0xffff0330 default value: 0x00000000 access: read only function: this 32-bit register holds the 32-bit value captured by an enabled irq event. timer1 control register name: t1con address: 0xffff0328 default value: 0x01000000 access: read/write function: this 32-bit mmr configures the timer1 mode of operation. table 54. t1con mmr bit designations bit description 31 to 24 8-bit postscaler. by writing to these eight bits, a value is written to the postscaler. writing 0 is interpreted as a 1. by reading these eight bits, the current value of the counter is read. 23 timer1 enable postscaler. set to enable the timer1 postscaler. if enabled, interrupts are generated after t1con[31:24] periods as defined by t1ld. cleared to disable the timer1 postscaler. 22 to 20 reserved. these bits are reserved and should be written as 0 by user code. 19 postscaler compare flag. read only. set if the number of timer1 overflows is eq ual to the number written to the postscaler. 18 timer1 interrupt source. set to select interrupt generati on from the postscaler counter. cleared to select interrupt generation directly from timer1. 17 event select bit. set by user to enable time capture of an event. cleared by user to disable time capture of an event. 16 to 12 event select range (0 to 17). the events are described in table 52 . 11 to 9 clock select. 000 = core clock (default). 001 = low power 32.768 khz oscillator. 010 = gpio_8. 011 = gpio_5. 8 count up. set by user for timer1 to count up. cleared by user for timer1 to count down (default). 7 timer1 enable bit. set by user to enable timer1. cleared by user to disable timer1 (default). 6 timer1 mode. set by user to operate in periodic mode. cleared by user to operate in free running mode (default). 5 to 4 format. 00 = binary (default). 01 = reserved. 10 = hours:minutes:seconds:hundredths (23 hours to 0 hours). 11 = hours:minutes:seconds:hundredths (255 hours to 0 hours). 3 to 0 prescaler. 0000 = source clock/1 (default). 0100 = source clock/16. 1000 = source clock/256. 1111 = source clock/32,768.
aduc7036 rev. b | page 77 of 132 timer2wake-up timer timer2 is a 32-bit wake-up up/down counter timer, with a pro- grammable prescaler. the prescaler is clocked directly from one of four clock sources: namely, the core clock (which is the default selection), the low power 32.768 khz oscillator, the external 32.768 khz watch crystal, or the precision 32.768 khz oscillator. the selected clock source can be scaled by a factor of 1, 16, 256, or 32,768. the wake-up timer continues to run when the core clock is disabled. when the core is operating at 20.48 mhz and at cd = 0 with a prescaler of 1, a minimum resolution of 48.83 ns results. the counter can be formatted as a plain 32-bit value or as time expressed as hours:minutes:seconds:hundredths. timer2 reloads the value from t2ld when timer2 overflows. the timer2 interface consists of four mmrs: t2ld, t2val, t2clri, and t2con. t2ld and t2val are 32-bit registers and hold 32-bit unsigned integers. t2val is a read only register. t2clri is an 8-bit register. writing any value to this register clears the timer2 interrupt. t2con is a configuration mmr and is described in table 5 5 . timer2 load register name: t2ld address: 0xffff0340 default value: 0x00000000 access: read/write function: this 32-bit register holds the 32-bit value that is loaded into the counter. timer2 clear register name: t2clri address: 0xffff034c access: write only function: this 8-bit, write only mmr is written (with any value) by user code to clear the interrupt. timer2 value register name: t2val address: 0xffff0344 default value: 0xffffffff access: read only function: this 32-bit register holds the current value of timer2. timer2 irq 32-bit up/down counter precision 32.768khz oscillator low power 32.768khz oscillator core clock 32-bit load prescaler 1, 16, 256, or 32,768 external 32.768khz watch crystal 7474-034 timer2 value 0 figure 36. timer2 block diagram
aduc7036 rev. b | page 78 of 132 timer2 control register name: t2con address: 0xffff0348 default value: 0x0000 access: read/write function: this 16-bit mmr configures the mode of operation of timer2. table 55. t2con mmr bit designations bit description 15 to 11 reserved. 10 to 9 clock source select. 00 = core clock (default). 01 = low power (32.768 khz) oscillator. 10 = external 32.768 khz watch crystal. 11 = precision 32.768 khz oscillator. 8 count up. set by user for timer2 to count up. cleared by user for timer2 to count down (default). 7 timer2 enable bit. set by user to enable timer2. cleared by user to disable timer2 (default). 6 timer2 mode. set by user to operate in periodic mode. cleared by user to operate in free running mode (default). 5 to 4 format. 00 = binary (default). 01 = reserved. 10 = hours:minutes:seconds:hundredths (23 hours to 0 hours). this is valid only with a 32 khz clock. 11 = hours:minutes:seconds:hundredths (255 hours to 0 hours). this is valid only with a 32 khz clock. 3 to 0 prescaler. 0000 = source clock/1 (default). 0100 = source clock/16. 1000 = source clock/256. this setting should be used in conjun ction with timer2 in the hours:minutes:seconds:hundredths format. see the 10 and 11 settings for the fo rmat bits (bits[5:4]) in this table. 1111 = source clock/32,768.
aduc7036 rev. b | page 79 of 132 timer3watchdog timer timer3 has two modes of operation: normal mode and watch- dog mode. the watchdog timer is used to recover from an illegal software state. when enabled, timer3 requires periodic servicing to prevent it from forcing a reset of the processor. timer3 reloads the value from t3ld when timer3 overflows. normal mode the timer3 in normal mode is identical to timer0 in 16-bit mode of operation, except for the clock source. the clock source is the low power 32.768 khz oscillator, which is scalable by a factor of 1, 16, or 256. watchdog mode watchdog mode is entered by setting t3con[5]. timer3 decrements from the timeout value present in the t3ld register until 0 is reached. the maximum timeout is 512 seconds, using a maximum prescaler/256 and full scale in t3ld. user software should not configure a timeout period of less than 30 ms to avoid any conflict with flash/ee memory page erase cycles that require 20 ms to complete a single page erase cycle and kernel execution. if t3val reaches 0, a reset or an interrupt occurs, depending on t3con[1]. to avoid a reset or an interrupt event, any value must be written to t3clri before t3val reaches 0. this reloads the counter with t3ld and begins a new timeout period. when watchdog mode is entered, t3ld and t3con are write protected. these two registers cannot be modified until a power-on reset event resets the watchdog timer. after any other reset event, the watchdog timer continues to count. the watchdog timer should be configured in the initial lines of user code to avoid an infinite loop of watchdog resets. user software should configure only a minimum timeout period of 30 ms. timer3 is automatically halted during jtag debug access and recommences counting only after jtag has relinquished control of the arm7 core. by default, timer3 continues to count during power-down. this can be disabled by setting bit 0 in t3con. it is recommended to use the default value; that is, the watchdog timer continues to count during power-down. timer3 interface the timer3 interface consists of four mmrs: t3ld, t3val, t3clri, and t3con. t3ld and t3val are 16-bit registers (bit 0 to bit 15) and hold 16-bit unsigned integers. t3val is a read only register. t3clri is an 8-bit register. writing any value to this register clears the timer3 interrupt in normal mode or resets a new timeout period in watchdog mode. t3con is the configuration mmr described in table 56 . timer3 load register name: t3ld address: 0xffff0360 default value: 0x0040 access: read/write function: this 16-bit mmr holds the timer3 reload value. timer3 clear register name: t3clri address: 0xffff036c access: write only function: this 8-bit, write only mmr is written (with any value) by user code to refresh (reload) timer3 in watchdog mode to prevent a watchdog timer reset event. timer3 value register name: t3val address: 0xffff0364 default value: 0x0040 access: read only function: this 16-bit, read only mmr holds the current timer3 count value. prescaler 1, 16, 256 timer3 irq watchdog reset 16-bit load 16-bit up/down counter low power 32.768khz timer3 value 07474-035 figure 37. timer3 block diagram
aduc7036 rev. b | page 80 of 132 timer 3 control register name: t3con address: 0xffff0368 default value: 0x0000 access: read/write function: the 16-bit mmr configures the timer3 mode of operation as described in table 56 . table 56. t3con mmr bit designations bit description 15 to 9 reserved. these bits are reserved and should be written as 0 by user code. 8 count up/count down enable. set by user code to configure timer3 to count up. cleared by user code to configure timer3 to count down. 7 timer3 enable. set by user code to enable timer3. cleared by user code to disable timer3. 6 timer3 operating mode. set by user code to configure timer3 to operate in periodic mode. cleared by user code to configure timer3 to operate in free running mode. 5 watchdog timer mode enable. set by user code to enable watchdog mode. cleared by user code to disable watchdog mode. 4 reserved. this bit is reserved and should be written as 0 by user code. 3 to 2 timer3 clock (32.768 khz) prescaler. 00 = source clock/1 (default). 01 = source clock/16. 10 = source clock/256. 11 = reserved. 1 watchdog timer irq enable. set by user code to produce an irq instead of a reset when the watchdog reaches 0. cleared by user code to disable the irq option. 0 pd_off. set by user code to stop timer3 when the peripher als are powered down using bit 4 in the powcon mmr. cleared by user code to enable timer3 when the peripherals are powered down using bit 4 in the powcon mmr.
aduc7036 rev. b | page 81 of 132 timer4sti timer timer4 is a general-purpose, 16-bit up/down counter timer with a programmable prescaler. timer4 can be clocked from the core clock or from the low power 32.768 khz oscillator with a prescaler of 1, 16, 256, or 32,768. timer4 has a capture register (t4cap) that can be triggered by the initial assertion of a selected irq source. after the capture register is triggered, the current timer value is copied to t4cap, and the timer continues running. this feature can be used to determine the assertion of an event with increased accuracy. timer4 can also be used to drive the serial test interface (sti) peripheral. the timer4 interface consists of five mmrs: t4ld, t4val, t4cap, t4clri, and t4con. t4ld, t4val, and t4cap are 16-bit registers that hold 16-bit unsigned integers. t4val and t4cap are read only. t4clri is an 8-bit register. writing any value to this register clears the interrupt. t4con is a configuration mmr and is described in table 5 7 . timer4 load register name: t4ld address: 0xffff0380 default value: 0x0000 access: read/write function: this 16-bit register holds the 16-bit value that is loaded into the counter. timer4 clear register name: t4clri address: 0xffff038c access: write only function: this 8-bit, write only mmr is written (with any value) by user code to clear the interrupt. timer4 value register name: t4val address: 0xffff0384 default value: 0xffff access: read only function: this 16-bit register holds the current value of timer4. time4 capture register name: t4cap address: 0xffff0390 default value: 0x0000 access: read only function: this 16-bit register holds the 32-bit value captured by an enabled irq event. timer4 control register name: t4con address: 0xffff0388 default value: 0x00000000 access: read/write function: this 32-bit mmr configures the mode of operation of timer4. prescaler 1, 16, 256, or 32,768 sti timer4 irq 16-bit load low power 32.768khz oscillator 16-bit up/down counter core clock frequency timer4 value capture irq[31:0] 07474-036 figure 38. timer4 block diagram
aduc7036 rev. b | page 82 of 132 table 57. t4con mmr bit designations bit description 31 to 18 reserved. 17 event select bit. set by user to enable time capture of an event. cleared by user to disable time capture of an event. 16 to 12 event select range (0 to 17). the events are described in table 52 . 11 to 10 reserved. 9 clock select. 0 = core clock (default). 1 = low power 32.768 khz oscillator. 8 count up. set by user for timer4 to count up. cleared by user for timer4 to count down (default). 7 timer4 enable bit. set by user to enable timer0. cleared by user to disable timer0 (default). 6 timer4 mode. set by user to operate in periodic mode. cleared by user to operate in free running mode (default). 5 to 4 reserved. 3 to 0 prescaler. 0000 = source clock/1 (default). 0100 = source clock/16. 1000 = source clock/256. 1111 = source clock/32,768.
aduc7036 rev. b | page 83 of 132 1 only available on gpio_0, gpio_5, gpio_7, and gpio_8. gpio dvdd general-purpose i/o the aduc7036 features nine general-purpose bidirectional input/ output (gpio) pins. in general, many of the gpio pins have multiple functions that can be configured by user code. by default, the gpio pins are configured in gpio mode. all gpio pins have an internal pull-up resistor with a sink capability of 0.8 ma and a source capability of 0.1 ma. the nine gpios are grouped into three ports: port0, port1, and port2. port0 is five bits wide. port1 and port2 are each two bits wide. the gpio assignment within each port is detailed in table 58 . a typical gpio structure is shown figure 39 . reg_ output drive enable gpxdat[31:24] output data gpxdat[23:16] input data gpxdat[7:0] gpio irq 1 07474-037 figure 39. typical gpio structure external interrupts are present on gpio_0, gpio_5, gpio_7, and gpio_8. these interrupts are level triggered and active high. these interrupts are not latched; therefore, the interrupt source must be present until either irqsta or fiqsta are interrogated. the interrupt source must be active for at least one cd-divided core clock to guarantee recognition. a ll port pins are configured and controlled by three sets (one set for each port) of four port-specific mmrs, as follows: ? gpxcon: portx control register ? gpxdat: portx configuration and data register ? gpxset: portx data set ? gpxclr: portx data clear where x corresponds to the port number (0, 1, or 2). during normal operation, user code can control the function and state of the external gpio pins using these general-purpose registers. all gpio pins retain their external level (high or low) during power-down (powcon) mode.
aduc7036 rev. b | page 84 of 132 table 58. external gpio pin to in ternal port signal assignments port gpio pin port signal functionality (defined by gpxcon) port0 gpio_0 p0.0 general-purpose i/o. irq0 external interrupt request 0. ss slave select i/o for spi. gpio_1 p0.1 general-purpose i/o. sclk serial clock i/o for spi. gpio_2 p0.2 general-purpose i/o. miso master input, slave output for spi. gpio_3 p0.3 general-purpose i/o. mosi master output, slave input for spi. gpio_4 p0.4 general-purpose i/o. eclk 2.56 mhz clock output. p 0 . 5 1 high voltage serial interface. p 0 . 6 1 high voltage serial interface. port1 gpio_5 p1.0 general-purpose i/o. irq1 external interrupt request 1. rxd pin for uart. gpio_6 p1.1 general-purpose i/o. txd pin for uart. port2 gpio_7 port 2.0 general-purpose i/o. irq4 external interrupt request 4. lin output pin 2 used to read directly from lin pin for conformance testing. gpio_8 p2.1 general-purpose i/o. irq5 external interrupt request 5. lin hv input pin 2 used to directly drive lin pin for conformance testing. gpio_11 2 p2.4 2 general-purpose i/o. linrx x 2 lin input pin. gpio_12 2 p2.5 2 general-purpose i/o. l i n t x x 2 lin output pin. gpio_13 1 p2.6 1 general-purpose i/o; sti data output. 1 these signals are internal signals only and do not appear on an external pin. these pins are used along with hvcon as the 2-wi re interface to the high voltage interface circuits. 2 these pins/signals are internal signals only and do not appear on an external pin. the signals are used to provide the externa l pin diagnostic write (gpio_12) and readback (gpio_ 11) capability.
aduc7036 rev. b | page 85 of 132 gpio port0 control register name: gp0con address: 0xffff0d00 default value: 0x11100000 access: read/write function: this 32-bit mmr selects the pin function for each port0 pin. table 59. gp0con mmr bit designations bit description 31 to 29 reserved. these bits are reserved and should be written as 0 by user code. 28 reserved. this bit is reserved and should be written as 1 by user code. 27 to 25 reserved. these bits are reserved and should be written as 0 by user code. 24 internal p0.6 enable bit. this bit must be set to 1 by user software to enable the high voltage serial interface before using the hvcon and hvdat registered high voltage interface. 23 to 21 reserved. these bits are reserved and should be written as 0 by user code. 20 internal p0.5 enable bit. this bit must be set to 1 by user software to enable the high voltage serial interface before using the hvcon and hvdat registered high voltage interface. 19 to 17 reserved. these bits are reserved and should be written as 0 by user code. 16 gpio_4 function select bit. set to 1 by user code to configure the gpio_4 pin as eclk, enabling a 2.56 mhz clock output on this pin. cleared by user code to 0 to configure the gpio_4 pin as a general-purpose i/o (gpio) pin. 15 to 13 reserved. these bits are reserved and should be written as 0 by user code. 12 gpio_3 function select bit. set to 1 by user code to configure the gpio_3 pin as mosi, master output, and slave input data for the spi port. cleared by user code to 0 to configure the gpio_3 pin as a general-purpose i/o (gpio) pin. 11 to 9 reserved. these bits are reserved and should be written as 0 by user code. 8 gpio_2 function select bit. set to 1 by user code to configure the gpio_2 pin as miso, master input and slave output data for the spi port. cleared by user code to 0 to configure the gpio_2 pin as a general-purpose i/o (gpio) pin. 7 to 5 reserved. these bits are reserved and should be written as 0 by user code. 4 gpio_1 function select bit. set to 1 by user code to configure the gpio_1 pin as sclk, serial clock i/o for the spi port. cleared by user code to 0 to configure the gpio_1 pin as a general-purpose i/o (gpio) pin. 3 to 1 reserved. these bits are reserved and should be written as 0 by user code. 0 gpio_0 function select bit. set to 1 by user code to configure the gpio_0 pin as ss , serial clock i/o for the spi port. cleared by user code to 0 to configure the gpio_0 pin as a general-purpose i/o (gpio) pin.
aduc7036 rev. b | page 86 of 132 gpio port1 control register name: gp1con address: 0xffff0d04 default value: 0x10000000 access: read/write function: this 32-bit mmr selects the pin function for each port1 pin. table 60. gp1con mmr bit designations bit description 31 to 5 reserved. these bits are reserved and should be written as 0 by user code. 4 gpio_6 function select bit. set to 1 by user code to configure the gpio_6 pi n as txd, transmit data for uart serial port. cleared by user code to 0 to configure the gpio_6 pin as a general-purpose i/o (gpio) pin. 3 to 1 reserved. these bits are reserved and should be written as 0 by user code. 0 gpio_5 function select bit. set by user code to 1 to configure the gpio_5 pin as rxd. receive data for uart serial port. cleared by user code to 0 to configure the gpio_5 pin as a general-purpose i/o (gpio) pin.
aduc7036 rev. b | page 87 of 132 gpio port2 control register name: gp2con address: 0xffff0d08 default value: 0x01000000 access: read/write function: this 32-bit mmr selects the pin function for each port2 pin. table 61. gp2con mmr bit designations bit description 31 to 25 reserved. these bits are reserved and should be written as 0 by user code. 24 gpio_13 function select bit. set to 1 by user code to route th e sti data output to the sti pin. if this bit is cleared to 0 by user code, then the sti data is not routed to the exte rnal sti pin even if the sti interface is enabled correctly. 23 to 21 reserved. these bits are reserved and should be written as 0 by user code. 20 gpio_12 function select bit. set to 1 by user code to route the uart txd (transmit data) to the lin/bsd data pin. this configuration is used in lin mode. cleared by user code to 0 to route the li n/bsd transmit data to an internal genera l-purpose i/o (gpio_12) pad, which can then be written via the gp2dat mmr. this configuration is used in bsd mode to allow user code to write output data to the bsd interface, and it can also be used to support diagnostic writ e capability to the high voltage i/o pins (see hvcfg1[2:0] in table 75 ). 19 to 17 reserved. these bits are reserved and should be written as 0 by user code. 16 gpio_11 function select bit. set to 1 by user code to route input data from the lin/bsd interface to both the lin/bsd hardware timing/synchronization logic and to the uart rxd (receive data). th is mode must be configured by user code when using lin or bsd modes. cleared by user code to 0 to internally disable the lin/bsd inp ut data path. in this configurat ion gpio_11 is used to support diagnostic readback on all external hi gh voltage i/o pins (see hvcfg1[2:0] in table 75 ). 15 to 5 reserved. these bits are reserved and should be written as 0 by user code. 4 gpio_8 function select bit. set to 1 by user code to route the lin/bs d input data to the gpio_8 pin. this mode can be used to drive the lin transceiver interface as a standalone component without any interaction from mcu or uart. cleared by user code to 0 to configure the gpio_8 pin as a general-purpose i/o (gpio) pin. 3 to 1 reserved. these bits are reserved and should be written as 0 by user code. 0 gpio_7 function select bit. set by user code to 1 to route data driven into the gpio_7 pi n through the on-chip lin transceiver to be output at the lin/bsd pin. this mode can be used to drive the lin transceiver interf ace as a standalone component without any interaction from mcu or uart. cleared by user code to 0 to configure the gpio_7 pin as a general-purpose i/o (gpio) pin.
aduc7036 rev. b | page 88 of 132 gpio port0 data register name: gp0dat address: 0xffff0d20 default value: 0x000000xx access: read/write function: this 32-bit mmr configures the direction of the gpio pins assigned to port0 (see table 58 ). this register also sets the output value for gpio pins configured as outputs and reads the status of gpio pins configured as inputs. table 62. gp0dat mmr bit designations bit description 31 to 29 reserved. these bits are reserved and should be written as 0 by user code. 28 port 0.4 direction select bit. set to 1 by user code to configure the gpio pin assigned to port 0.4 as an output. cleared to 0 by user code to configure the gpio pin assigned to port 0.4 as an input. 27 port 0.3 direction select bit. set to 1 by user code to configure the gp io pin assigned to port 0.3 as an output. cleared to 0 by user code to configure the gpio pin assigned to port 0.3 as an input. 26 port 0.2 direction select bit. set to 1 by user code to configure the gp io pin assigned to port 0.2 as an output. cleared to 0 by user code to configure the gpio pin assigned to port 0.2 as an input. 25 port 0.1 direction select bit. set to 1 by user code to configure the gpio pin assigned to port 0.1 as an output. cleared to 0 by user code to configure the gpio pin assigned to port 0.1 as an input. 24 port 0.0 direction select bit. set to 1 by user code to configure the gpio pin assigned to port 0.0 as an output. cleared to 0 by user code to configure the gpio pin assigned to port 0.0 as an input. 23 to 21 reserved. these bits are reserved and should be written as 0 by user code. 20 port 0.4 data output. the value written to this bit ap pears directly on the gpio pin assigned to port 0.4. 19 port 0.3 data output. the value written to this bit ap pears directly on the gpio pin assigned to port 0.3. 18 port 0.2 data output. the value written to this bit ap pears directly on the gpio pin assigned to port 0.2. 17 port 0.1 data output. the value written to this bit ap pears directly on the gpio pin assigned to port 0.1. 16 port 0.0 data output. the value written to this bit ap pears directly on the gpio pin assigned to port 0.0. 15 to 5 reserved. these bits are reserved and should be written as 0 by user code. 4 port 0.4 data input. this bit is a read on ly bit that reflects the current status of the gpio pin assigned to port 0.4. user co de should write 0 to this bit. 3 port 0.3 data input. this bit is a read on ly bit that reflects the current status of the gpio pin assigned to port 0.3. user co de should write 0 to this bit. 2 port 0.2 data input. this bit is a read on ly bit that reflects the current status of the gpio pin assigned to port 0.2. user co de should write 0 to this bit. 1 port 0.1 data input. this bit is a read on ly bit that reflects the current status of the gpio pin assigned to port 0.1. user co de should write 0 to this bit. 0 port 0.0 data input. this bit is a read on ly bit that reflects the current status of the gpio pin assigned to port 0.0. user co de should write 0 to this bit.
aduc7036 rev. b | page 89 of 132 gpio port1 data register name: gp1dat address: 0xffff0d30 default value: 0x000000xx access: read/write function: this 32-bit mmr configures the direction of the gpio pins assigned to port1 (see table 58 ). this register also sets the output value for gpio pins configured as outputs and reads the status of gpio pins configured as inputs. table 63. gp1dat mmr bit designations bit description 31 to 26 reserved. these bits are reserved and should be written as 0 by user code. 25 port 1.1 direction select bit. set to 1 by user code to configure the gpio pin assigned to port 1.1 as an output. cleared to 0 by user code to configure the gpio pin assigned to port 1.1 as an input. 24 port 1.0 direction select bit. set to 1 by user code to configure the gpio pin assigned to port 1.0 as an output. cleared to 0 by user code to configure the gpio pin assigned to port 1.0 as an input. 23 to 18 reserved. these bits are reserved and should be written as 0 by user code. 17 port 1.1 data output. the value written to this bit ap pears directly on the gpio pin assigned to port 1.1. 16 port 1.0 data output. the value written to this bit ap pears directly on the gpio pin assigned to port 1.0. 15 to 2 reserved. these bits are reserved and should be written as 0 by user code. 1 port 1.1 data input. this bit is a read on ly bit that reflects the current status of the gpio pin assigned to port 1.1. user co de should write 0 to this bit. 0 port 1.0 data input. this bit is a read on ly bit that reflects the current status of the gpio pin assigned to port 1.0. user co de should write 0 to this bit.
aduc7036 rev. b | page 90 of 132 gpio port2 data register name: gp2dat address: 0xffff0d40 default value: 0x000000xx access: read/write function: this 32-bit mmr configures the direction of the gpio pins assigned to port2 (see table 58 ). this register also sets the output value for gpio pins configured as outputs and reads the status of gpio pins configured as inputs. table 64. gp2dat mmr bit designations bit description 31 reserved. this bit is reserved and should be written as 0 by user code. 30 port 2.6 direction select bit. set to 1 by user code to configure the gpio pin assigned to port 2.6 as an output. cleared to 0 by user code to configure the gpio pin assigned to port 2.6 as an input 29 port 2.5 direction select bit. set to 1 by user code to configure the gpio pin assigned to port 2.5 as an output. this configuration is used to support diagnostic write capability to the high voltage i/o pins. cleared to 0 by user code to configure the gpio pin assigned to port 2.5 as an input. 28 port 2.4 direction select bit. set to 1 by user code to configure the gpio pin assigned to port 2.4 as an output. cleared to 0 by user code to configure the gpio pin assigned to port 2.4 as an input. this configuration is used to support diagnostic readback capability from the high voltage i/o pins (see hvcfg1[2:0]). 27 to 26 reserved. these bits are reserved and should be written as 0 by user code. 25 port 2.1 direction select bit. set to 1 by user code to configure the gpio pin assigned to port 2.1 as an output. cleared to 0 by user code to configure the gpio pin assigned to port 2.1 as an input. 24 port 2.0 direction select bit. set to 1 by user code to configure the gp io pin assigned to port 2.0 as an output. cleared to 0 by user code to configure the gpio pin assigned to port 2.0 as an input. 23 reserved. this bit is reserved and should be written as 0 by user code. 22 port 2.6 data output. the value written to this bit ap pears directly on the gpio pin assigned to port 2.6. 21 port 2.5 data output. the value written to this bit ap pears directly on the gpio pin assigned to port 2.5. 20 to 18 reserved. these bits are reserved and should be written as 0 by user code. 17 port 2.1 data output. the value written to this bit ap pears directly on the gpio pin assigned to port 2.1. 16 port 2.0 data output. the value written to this bit ap pears directly on the gpio pin assigned to port 2.0. 15 to 7 reserved. these bits are reserved and should be written as 0 by user code. 6 port 2.6 data input. this bit is a read on ly bit that reflects the current status of the gpio pin assigned to port 2.6. user co de should write 0 to this bit. 5 port 2.5 data input. this bit is a read on ly bit that reflects the current status of the gpio pin assigned to port 2.5. user co de should write 0 to this bit. 4 port 2.4 data input. this bit is a read on ly bit that reflects the current status of the gpio pin assigned to port 2.4. user co de should write 0 to this bit. 3 to 2 reserved. these bits are reserved and should be written as 0 by user code. 1 port 2.1 data input. this bit is a read on ly bit that reflects the current status of the gpio pin assigned to port 2.1. user co de should write 0 to this bit. 0 port 2.0 data input. this bit is a read on ly bit that reflects the current status of the gpio pin assigned to port 2.0. user co de should write 0 to this bit.
aduc7036 rev. b | page 91 of 132 gpio port0 set register name: gp0set address: 0xffff0d24 access: write only function: this 32-bit mmr allows user code to individually bit-ad dress external gpio pins to set them high only. user code can accomplish this using the gp0set mmr without having to modify or maintain the status of the gpio pins (as user code requires when using gp0dat). table 65. gp0set mmr bit designations bit description 31 to 21 reserved. these bits are reserved and should be written as 0 by user code. 20 port 0.4 set bit. set to 1 by user code to se t the external gpio_4 pin high. clearing this bit to 0 via user software has no effect on the external gpio_4 pin. 19 port 0.3 set bit. set to 1 by user code to set the external gpio_3 pin high. clearing this bit to 0 via user software has no effect on the external gpio_3 pin. 18 port 0.2 set bit. set to 1 by user code to set the external gpio_2 pin high. clearing this bit to 0 via user software has no effect on the external gpio_2 pin. 17 port 0.1 set bit. set to 1 by user code to set the external gpio_1 pin high. clearing this bit to 0 via user software has no effect on the external gpio_1 pin. 16 port 0.0 set bit. set to 1 by user code to se t the external gpio_0 pin high. clearing this bit to 0 via user software has no effect on the external gpio_0 pin. 15 to 0 reserved. these bits are reserved and should be written as 0 by user code. gpio port1 set register name: gp1set address: 0xffff0d34 access: write only function: this 32-bit mmr allows user code to individually bit-address external gpio pins to set them high only. user code can accomplish this using the gp1set mmr without having to modify or maintain the status of the gpio pins (as user code requires when using gp1dat). table 66. gp1set mmr bit designations bit description 31 to 18 reserved. these bits are reserved and should be written as 0 by user code. 17 port 1.1 set bit. set to 1 by user code to se t the external gpio_6 pin high. clearing this bit to 0 via user software has no effect on the external gpio_6 pin. 16 port 1.0 set bit. set to 1 by user code to set the external gpio_5 pin high. clearing this bit to 0 via user software has no effect on the external gpio_5 pin. 15 to 0 reserved. these bits are reserved and should be written as 0 by user code.
aduc7036 rev. b | page 92 of 132 gpio port2 set register name: gp2set address: 0xffff0d44 access: write only function: this 32-bit mmr allows user code to individually bit-address external gpio pins to set them high only. user code can accomplish this using the gp2set mmr without having to modify or maintain the status of the gpio pins (as user code requires when using gp2dat) . table 67. gp2set mmr bit designations bit description 31 to 23 reserved. these bits are reserved and should be written as 0 by user code. 22 port 2.6 set bit. set to 1 by user code to se t the external gpio_13 pin high. clearing this bit to 0 via user software has no effect on the external gpio_13 pin. 21 port 2.5 set bit. set to 1 by user code to se t the external gpio_12 pin high. clearing this bit to 0 via user software has no effect on the external gpio_12 pin. 20 to 18 reserved. these bits are reserved and should be written as 0 by user code. 17 port 2.1 set bit. set to 1 by user code to set the external gpio_8 pin high. clearing this bit to 0 via user software has no effect on the external gpio_8 pin. 16 port 2.0 set bit. set to 1 by user code to set the external gpio_7 pin high. clearing this bit to 0 via user software has no effect on the external gpio_7 pin. 15 to 0 reserved. these bits are reserved and should be written as 0 by user code. gpio port0 clear register name: gp0clr address: 0xffff0d28 access: write only function: this 32-bit mmr allows user code to individually bit-address external gpio pins to clear them low only. user code can accomplish this using the gp0clr mmr without having to modify or maintain the status of the gpio pins (as user code requires when using gp 0dat). table 68. gp0clr mmr bit designations bit description 31 to 21 reserved. these bits are reserved and should be written as 0 by user code. 20 port 0.4 clear bit. set to 1 by user code to clear the external gpio_4 pin low. clearing this bit to 0 via user software has no effect on the external gpio_4 pin. 19 port 0.3 clear bit. set to 1 by user code to clear the external gpio_3 pin low. clearing this bit to 0 via user software has no effect on the external gpio_3 pin. 18 port 0.2 clear bit. set to 1 by user code to clear the external gpio_2 pin low. clearing this bit to 0 via user software has no effect on the external gpio_2 pin. 17 port 0.1 clear bit. set to 1 by user code to clear the external gpio_1 pin low. clearing this bit to 0 via user software has no effect on the external gpio_1 pin. 16 port 0.0 clear bit. set to 1 by user code to clear the external gpio_0 pin low. clearing this bit to 0 via user software has no effect on the external gpio_0 pin. 15 to 0 reserved. these bits are reserved and should be written as 0 by user code.
aduc7036 rev. b | page 93 of 132 gpio port1 clear register name: gp1clr address: 0xffff0d38 access: write only function: this 32-bit mmr allows user code to individually bit-address external gpio pins to clear them low only. user code can accomplish this using the gp1clr mmr without having to modify or maintain the status of the gpio pins (as user code requires when using gp 1dat). table 69. gp1clr mmr bit designations bit description 31 to 18 reserved. these bits are reserved and should be written as 0 by user code. 17 port 1.1 clear bit. set to 1 by user code to clear the external gpio_6 pin low. clearing this bit to 0 via user software has no effect on the external gpio_6 pin. 16 port 1.0 clear bit. set to 1 by user code to clear the external gpio_5 pin low. clearing this bit to 0 via user software has no effect on the external gpio_5 pin. 15 to 0 reserved. these bits are reserved and should be written as 0 by user code. gpio port2 clear register name: gp2clr address: 0xffff0d48 access: write only function: this 32-bit mmr allows user code to individually bit-address external gpio pins to clear them low only. user code can accomplish this using the gp2clr mmr without having to modify or maintain the status of the gpio pins (as user code requires when using gp 2dat). table 70. gp2clr mmr bit designations bit description 31 to 23 reserved. these bits are reserved and should be written as 0 by user code. 22 port 2.6 clear bit. set to 1 by user code to clear the external gpio_13 pin low. clearing this bit to 0 via user software has no effect on the external gpio_8 pin. 21 port 2.5 clear bit. set to 1 by user code to clear the external gpio_12 pin low. clearing this bit to 0 via user software has no effect on the external gpio_7 pin. 20 to 18 reserved. these bits are reserved and should be written as 0 by user code. 17 port 2.1 clear bit. set to 1 by user code to clear the external gpio_8 pin low. clearing this bit to 0 via user software has no effect on the external gpio_8 pin. 16 port 2.0 clear bit. set to 1 by user code to clear the external gpio_7 pin low. clearing this bit to 0 via user software has no effect on the external gpio_7 pin. 15 to 0 reserved. these bits are reserved and should be written as 0 by user code.
aduc7036 rev. b | page 94 of 132 high voltage peripheral control interface the aduc7036 integrates several high voltage circuit functions that are controlled and monitored through a registered interface consisting of two mmrs: hvcon and hvdat. the hvcon register acts as a command byte interpreter, allowing the microcontroller to indirectly read or write 8-bit data (the value in hvdat) from or to one of four high voltage status or confi- guration registers. these high voltage registers are not mmrs but are registers commonly referred to as indirect registers; that is, they can be accessed (as the name suggests) only indirectly via the hvcon and hvdat mmrs. the physical interface between the hvcon register and the indirect high voltage registers is a 2-wire (data and clock) serial interface based on a 2.56 mhz serial clock. therefore, there is a finite, 10 s (maximum) latency between the mcu core writing a command into hvcon and that command or data reaching the indirect high voltage registers. there is also a finite 10 s latency between the mcu core writing a command into hvcon and the indirect register data being read back into the hvdat register. a busy bit (for example, bit 0 of the hvcon when read by mcu) can be polled by the mcu to confirm when a read/write command is complete. t he following high voltage circuit functions are controlled and monitored via this interface. figure 40 shows the top-level architecture of the high voltage interface and the following related circuits: ? precision oscillator ? wake-up (wu) pin functionality ? power supply monitor (psm) ? low voltage flag (lvf) ? lin operating modes ? sti diagnostics ? high voltage diagnostics ? high voltage attenuator buffers circuit ? high voltage (hv) temperature monitor arm7 mcu and peripherals high voltage interface mmrs hvcon hvdat hvcfg0 (indirect) high voltage registers precision oscillator hvcfg0[6] lvf hvcfg0[2] lin modes psm hvcfg0[3] attenuator and buffer hvcfg1[5] hvcfg1[7] hv temp monitor hvcfg1[6] hvcfg1[3] hvcfg1 hvsta hvmon serial data serial interface controller serial clock psm?hvsta[5] wu?hvsta[4] high voltage interrupt controller over temp?hvsta[3] lin s-sct?hvsta[2] sti s-sct?hvsta[1] wu s-sct?hvsta[0] irq3 (irqen[16]) hvcfg0[5] hvcfg0[1:0] high voltage diagnostic controller wu diagnostic input hvcfg0[4] sti diagnostic input p2.6 lin diagnostic input p2.5 wu diagnostic output hvmon[7] sti diagnostic output hvmon[5] lin diagnostic output p2.4 wu cont i/o rol hvcfg0[4] hvcfg1[4] hvcfg1[4] sti cont i/o rol hvcfg1[3] 07474-038 figure 40. high voltage interface, top-level block diagram
aduc7036 rev. b | page 95 of 132 high voltage interface control register name: hvcon address: 0xffff0804 default value: updated by kernel access: read/write function: this 8-bit register acts as a command byte interpreter for the high voltage control interface. bytes written to this register are interpreted as read or write commands to a set of four indirect registers related to the high voltage circuits. the hvdat regis ter is used to store data to be written to, or read back from, the indirect registers. table 71. hvcon mmr write bit designations bit description 7 to 0 command byte. interpreted as 0x00 = read back high voltage register hvcfg0 into hvdat. 0x01 = read back high voltage register hvcfg1 into hvdat. 0x02 = read back high voltage status register hvsta into hvdat. 0x03 = read back high voltage status register hvmon into hvdat. 0x08 = write the value in hvdat to the high voltage register hvcfg0. 0x09 = write the value in hvdat to the high voltage register hvcfg1. table 72. hvcon mmr read bit designations bit description 7 to 3 reserved. 2 transmit command to high voltage die status. 1 = command completed successfully. 0 = command failed. 1 read command from high voltage die status. 1 = command completed successfully. 0 = command failed. 0 busy bit (read only). when user code reads this register, bit 0 should be interpreted as the busy signal for the high voltage interface. this bit can be used to determine if a read re quest has completed. high voltage (read/write) commands as described in this table should not be written to hvcon unless busy = 0. busy = 1, high voltage interface is busy and has not comp leted the previous command written to hvcon. bit 1 and bit 2 are not valid. busy = 0, high voltage interface is not busy and has comple ted the command written to hvcon. bit 1 and bit 2 are valid.
aduc7036 rev. b | page 96 of 132 high voltage data register name: hvdat address: 0xffff080c default value: updated by kernel access: read/write function: this 12-bit register holds data to be written indirectly to, and read indirectly from, the following high voltage int erface registers. table 73. hvdat mmr bit designations bit description 11 to 8 command with which high voltage data hvdat[7:0] is associated. these bits are read only and should be written as 0s. 0x00 = read back high voltage register hvcfg0 into hvdat. 0x01 = read back high voltage register hvcfg1 into hvdat. 0x02 = read back high voltage status register hvsta into hvdat. 0x03 = read back high voltage status register hvmon into hvdat. 0x08 = write the value in hvdat to the high voltage register hvcfg0. 0x09 = write the value in hvdat to the high voltage register hvcfg1. 7 to 0 high voltage data to read/write.
aduc7036 rev. b | page 97 of 132 high voltage configuration0 register name: hvcfg0 address: indirectly addressed via the hvcon high voltage interface default value: 0x00 access: read/write function: this 8-bit register controls the function of high volt age circuits on the aduc7036. this register is not an mmr and d oes not appear in the mmr memory map. it is accessed via the hvcon register interface. data to be written to this register is loaded vi a the hvdat mmr, and data is read back from this register via the hvdat mmr. table 74. hvcfg0 bit designations bit description 7 wake-up/sti thermal shutdown disable. set to 1 to disable the automatic shutdown of th e wake-up/sti driver when a thermal event occurs. cleared to 0 to enable the automatic shutdown of the wake-up/sti driver when a thermal event occurs. 6 precision oscillator enable bit. set to 1 to enable the precision 131 khz oscillator. the oscill ator start-up time is typically 70 s (including a high voltage interface latency of 10 s). cleared to 0 to power down the precision 131 khz oscillator. 5 bit serial device (bsd) mode enable bit. set to 1 to disable the internal (lin) pull-up and configure the lin/bsd pin for bsd operation. cleared to 0 to enable the internal (lin) pull-up resistor on the lin/bsd pin. 4 wake-up (wu) assert bit. set to 1 to assert the external wu pin high. cleared to 0 to pull the external wu pin low via an internal 10 k pull-down resistor. 3 power supply monitor (psm) enable bit. set to 1 to enable the power supply (voltage at the vdd pin) monitor. if irq3 (irqen[16]) is enabled, the psm generates an interrupt if the voltage at the vdd pin drops below 6 v. cleared to 0 to disable the power supp ly (voltage at the vdd pin) monitor. 2 low voltage flag (lvf) enable bit. set to 1 to enable the lvf function. the low voltage fl ag can be interrogated via hvmon[3] after power-up to determine if the reg_dvdd voltage previously dropped below 2.1 v. cleared to 0 to disable the lvf function. 1 to 0 lin operating mode. these bits enable/disable the lin driver. 00 = lin disabled. 01 = reserved (not lin v2.0 compliant). 10 = lin enabled. 11 = reserved, not used.
aduc7036 rev. b | page 98 of 132 high voltage configuration1 register name: hvcfg1 address: indirectly addressed via the hvcon high voltage interface default value: 0x00 access: read/write function: this 8-bit register controls the function of high volt age circuits on the aduc7036. this register is not an mmr and d oes not appear in the mmr memory map. it is accessed via the hvcon register interface. data to be written to this register is loaded th rough hvdat, and data is read back from this register using hvdat. table 75. hvcfg1 bit designations bit description 7 voltage attenuator diagnostic enable bit. set to 1 to turn on a 1.29 a current source that adds 170 mv differential voltage to the voltage channel measurement. cleared to 0 to disable the voltage attenuator diagnostic. 6 high voltage temperature monitor. the high voltage temp erature monitor is an uncalibrated temperature monitor located on chip, close to the high voltage circuits. this monitor is completely separate to the on-chip, precision temperature sensor (controlled via adc1con[7:6]) and allows user code to monitor die temperature change close to the hottest part of the aduc7036 die. the monitor genera tes a typical output voltage of 600 mv at 25c and has a negative temperature coefficient of typically ?2.1 mv/c. set to 1 to enable the on-chip, high voltage temperatur e monitor. when enabled, this voltage output temperature monitor is routed directly to the voltage channel adc. cleared to 0 to disable the on-chip, high voltage temperature monitor. 5 voltage channel short enable bit. set to 1 to enable an internal short (at the attenuator, befo re the adc input buffers) on the voltage channel adc and to allow noise to be measured as a self-diagnostic test. cleared to 0 to disable an internal short on the voltage channel. 4 wu and sti readback enable bit. set to 1 to enable input capability on the external wu and st i pins. in this mode, a rising or falling edge transition on the wu and sti pins generates a high volt age interrupt. when this bit is set, th e state of the wu and sti pins can be monitored via the hvmon register (hvmon[7] and hvmon[5]). cleared to 0 to disable input capability on the external wu and sti pins. 3 high voltage i/o driver enable bit. set to 1 to reenable high voltage i/o pins (lin/bsd, sti, and wu) that have been disabled as a result of a short-circuit current event (the event must last longer than 20 s for the lin/bsd and sti pins and longer than 400 s for the wu pin). this bit must also be set to 1 to reenable the wu and sti pins if they were disabled by a thermal event. it should be noted that this bit must be set to clear any pending inte rrupt generated by the short-circuit event (even if the event has passed) as well as reenabling the high voltage i/o pins. cleared to 0 automatically. 2 enable/disable short-circuit protection (lin/bsd and sti). set to 1 to enable passive short-circuit protection on the li n pin. in this mode, a short-circuit event on the lin/bsd pin generates a high voltage interrupt, irq3 (if enabled in irqe n[16]), and asserts the appropria te status bit in hvsta but does not disable the short-circuiting pin. cleared to 0 to enable active short-circuit protection on the lin/bsd pin. in this mode, during a short-circuit event, the lin/bsd pin generates a high voltage interrupt (irq3), asserts hvsta[16], and automatically disables the short- circuiting pin. when disabled, the i/o pin can only be reenabled by writing to hvcfg1[3]. 1 wu pin timeout (monoflop) counter enable/disable. set to disable the wu i/o timeout counter. cleared to enable a timeout counter that automatically deasserts the wu pin 1.3 sec after user code has asserted the wu pin via hvcfg0[4]. 0 wu open-circuit diagnostic enable. set to enable an internal wu i/o diagnostic pull-up resistor to the vdd pin, thus allowing detection of an open-circuit condition on the wu pin. cleared to disable an internal wu i/o diagnostic pull-up resistor.
aduc7036 rev. b | page 99 of 132 high voltage monitor register name: hvmon address: indirectly addressed via the hvcon high voltage interface default value: 0x00 access: read only function: this 8-bit, read only register reflects the current status of enabled high voltage related circuits and functions on the aduc7036. this register is not an mmr and does not appear in the mmr memory map. it is accessed via the hvcon register interface, and dat a is read back from this register via hvdat. table 76. hvmon bit designations bit description 7 wu pin diagnostic readback. when enabled via hvcfg1[4], this read only bit reflects the state of the external wu pin. 6 overtemperature. 0 = a thermal shutdown event has not occurred. 1 = a thermal shutdown event has occurred. 5 sti pin diagnostic readback. when enabled via hvcfg1[4], this read only bit reflects the state of the external sti pin. 4 buffer enabled. 0 = the voltage channel adc input buffer is disabled. 1 = the voltage channel adc input buffer is enabled. 3 low voltage flag status bit. valid only if enabled via hvcfg0[2]. 0 (at power-on) = reg_dvdd has dropped below 2.1 v. in this state, ram contents can be deemed corrupt. 1 (at power-on) = reg_dvdd has not dropped below 2.1 v. in this state, ram contents can be deemed valid. it is only cleared by reenabling the low voltage flag in hvcfg0[2]. 2 lin/bsd short-circuit status flag. 0 = the lin/bsd driver is operating normally. 1 = the lin/bsd driver has experienced a short-circuit condit ion and is cleared automaticall y by writing to hvcfg1[3]. 1 sti short-circuit status flag. 0 = the sti driver is operating normally. 1 = the sti driver has experienced a short-circuit conditio n and is cleared automatically by writing to hvcfg1[3]. 0 wake-up short-circuit status flag. 0 = the wake-up driver is operating normally. 1 = the wake-up driver has experienced a short-circuit condition.
aduc7036 rev. b | page 100 of 132 high voltage status register name: hvsta address: indirectly addressed via the hvcon high voltage interface default value: 0x00 access: read only, this register should only be read on a high voltage interrupt function: this 8-bit, read only register reflects a change of state for all the corresponding bits in the hvmon register. this register is not an mmr and does not appear in the mmr memory map. it is accessed through the hvcon registered interface, and data is read back from this register via hvdat. in response to a high voltage interrupt event, the high voltage interrupt controller simultaneous ly and automatically loads the current value of the high voltage status register (hvsta) into the hvdat register. table 77. hvsta bit designations bit description 7 to 6 reserved. these bits should not be used and are reserved for future use. 5 psm status bit. valid only if enabled via hvcfg0[3]. this bit is not latched and the irq needs to be enabled to detect it. 0 = the voltage at the vdd pin stays above 6 v. 1 = the voltage at the vdd pin drops below 6 v. 4 wu request status bit. valid only if enabled via hvcfg1[4]. 0 = the wu pin has not generated a high voltage interrupt. 1 = a rising or falling edge transition on the wu pin gene rated a high voltage interrupt (when enabled via hvcfg1[4]). 3 overtemperature. this bit is always enabled. 0 = a thermal shutdown event has not occurred. 1 = a thermal shutdown event has occurred. all high voltage (lin/bsd, wu, and sti) pin drivers are automatically disabled once a thermal shutdown has occurred. 2 lin/bsd short-circuit status flag. 0 = normal lin/bsd operation. cleared auto matically by reading the hvsta register. 1 = a lin/bsd short circuit is detected. in this condition, the lin driver is automatically disabled. 1 sti short-circuit status flag. 0 = normal sti driver operation. cleared au tomatically by reading the hvsta register. 1 = the sti driver has experienced a short-circuit condition. 0 wake-up short-circuit status flag. 0 = normal wake-up operation. 1 = a wake-up short-circuit is detected.
aduc7036 rev. b | page 101 of 132 wake-up (wu) pin the wake-up (wu) pin is a high voltage gpio controlled through hvcon and hvdat. wake-up (wu) pin circuit description by default, the wu pin is configured as an output with an internal 10 k pull-down resistor and high-side fet driver. in its default mode of operation, the wu pin is specified to generate an active high system wake-up request by forcing the external system wu bus high. user code can assert the wu output by writing directly to hvcfg0[4]. note that the output responds only after a 10 s latency has elapsed; this latency is inherent in a serial communication between the hvcon or hvdat mmr and the high voltage interface (see the high voltage peripheral control interface section). the internal fet is capable of sourcing significant current; therefore, substantial on-chip self-heating may occur if this driver is asserted for a long time period. for this reason, a monoflop (that is, a 1.3 sec timeout timer) is included. by default, the monoflop is enabled and disables the wake-up driver after 1.3 sec. it is possibl e to disable the monoflop through hvcfg1[1]. if the wake-up monoflop is disabled, the wake-up driver should be disabled after 1.3 sec. the wu pin also features a short-circuit detection feature. when the wake-up pin sources more than 100 ma typically for 400 s, a high voltage interrupt is generated, and hvmon[0] is set. a thermal shutdown event disables the wu driver. the wu driver must be reenabled manually after using hvcfg1[3] after a thermal event. the wu pin can be configured in i/o mode by writing a 1 to hvcfg1[4]. in this mode, a rising or falling edge immediately generates a high voltage interrupt. hvmon[7] directly reflects the state of the external wu pin and indicates if the external wake-up bus (including r load = 1 k, c load = 91 nf, and r limit = 39 ) is above or below a typical voltage of 3 v. v dd internal sense resistor short-circuit trip reference short-circuit protection output control hvmon[0] 400s glitch immunity normal hvcfg0[4] normal hvmon[7] ~1v enable readback hvcfg1[4] internal 10k ? resistor r1 6.6k ? r2 3.3k ? io_vss 6k? open-circuit diagnostic resistor external wu pin external wake-up bus c load 91nf r load 1k? external current-limit resistor 39? hvcfg1[0] 07474-039 figure 41. wu circuit, block diagram
aduc7036 rev. b | page 102 of 132 handling interrupts from the high voltage peripheral control interface an interrupt controller is integrated with the high voltage circuits. if the interrupt controller is enabled through irqen[16], one of six high voltage sources can assert the high voltage interrupt (irq3) signal and interrupt the mcu core. although the normal mcu response to this interrupt event is to vector to the irq or fiq vector address, the high voltage interrupt controller simultaneously and automatically loads the current value of the high voltage status register (hvsta) into the hvdat register. during this time, the busy bit in hvcon[0] is set to indicate that a transfer is in progress and then is cleared after 10 s to indicate the hvsta contents are available in hvdat. the interrupt handler, therefore, can poll the busy bit in hvcon until it deasserts. after the busy bit is cleared, hvcon[1] must be checked to ensure that the data was read correctly. next, the hvdat register can be read. at this time, hvdat holds the value of the hvsta register. the status flags can then be interrogated to determine the exact source of the high voltage interrupt, and the appropriate action can be taken. low voltage flag (lvf) the aduc7036 features a low voltage flag (lvf) that allows the user to monitor reg_dvdd. when enabled via hvcfg0[2], the low voltage flag can be monitored through hvmon[3]. if reg_dvdd drops below 2.1 v, hvmon[3] is cleared and the ram contents are corrupted. after the low voltage flag is enabled, it is reset only by reg_dvdd dropping below 2.1 v or by disabling the lvf functionality using hvcfg0[2]. high voltage diagnostics it is possible to diagnosis fault conditions on the wu, lin, and sti pins, as described in table 78 . table 78. high voltage diagnostics high voltage pin fault condition method result lin or sti short between lin or sti and vbat drive lin or sti low lin or sti short-circuit interrupt is generated after 20 s if more than 100 ma is continuously drawn. short between lin or sti and gnd drive lin or sti high lin or sti readback reads back low. wu short between wake-up and vbat drive wu low readback high in hvmon[7]. short between wake-up and gnd drive wu high wu short-circuit interrupt is generated after 400 s if more than 100 ma typically is sourced. open circuit enable oc diagnostic resistor with wu disabled hvmon[7] is cleared if the load is connected and set if wu is open-circuited.
aduc7036 rev. b | page 103 of 132 uart serial interface the aduc7036 features a 16,450-compatible uart. the uart is a full-duplex, universal, asynchronous receiver/transmitter. a uart performs serial-to-parallel conversion on data characters received from a peripheral device and performs parallel-to-serial conversion on data characters received from the arm7tdmi. the uart features a fractional divider that facilitates high accu- racy baud rate generation and a network addressable mode. the uart functionality is available on the gpio_5/irq1/rxd and gpio_6/ txd pins of the aduc7036. the serial communication adopts an asynchronous protocol that supports various word lengths, stop bits, and parity generation options selectable in the configuration register. baud rate generation the aduc7036 features two methods of generating the uart baud rate: normal 450 uart baud rate generation and aduc7036 fractional divider baud rate generation. normal 450 uart baud rate generation the baud rate is a divided version of the core clock using the value in comdiv0 and comdiv1 mmrs (each is a 16-bit value, dl). the standard baud rate generator formula is dl ratebaud cd = 2162 mhz48.20 (1) table 79 lists common baud rate values. table 79. baud rate using the standard baud rate generator baud rate (bps) cd dl actual baud rate % error 9600 0 0x43 9552 0.50% 19,200 0 0x21 19,394 1.01% 115,200 0 0x6 106,667 7.41% 9600 3 0x8 10,000 4.17% 19,200 3 0x4 20,000 4.17% 115,200 3 0x1 80,000 30.56% fractional divider the fractional divider, combined with the normal baud rate generator, allows the generation of accurate, high speed baud rates. /2 /(m+n/2048) /16dl uart core clock fben 07474-040 figure 42. fractional divider baud rate generation calculation of the baud rate using a fractional divider is as follows: ) 2048 (2162 mhz48.20 n mdl ratebaud cd + = (2) 2162 mhz48.20 2048 =+ dl ratebaud n m cd where: cd is the clock divider. dl is the divisor latch. m is the integer part of the divisor; a fractional divider divides an input by a nonwhole number, m.n. n is the fractional part of the divisor; a fractional divider divides an input by a nonwhole number, m.n. table 80 lists common baud rate values. table 80. baud rate using the fractional baud rate generator baud rate (bps) cd dl m n actual baud rate % error 9600 0 0x42 1 21 9598.55 0.015% 19,200 0 0x21 1 21 19,197.09 0.015% 115,200 0 0x5 1 228 115,177.51 0.0195%
aduc7036 rev. b | page 104 of 132 uart register definitions t he uart interface consists of the following registers: ? comtx: 8-bit transmit register ? comrx: 8-bit receive register ? comdiv0: divisor latch (low byte) ? comdiv1: divisor latch (high byte) ? comcon0: line control register ? comcon1: line control register ? comsta0: line status register ? comien0: interrupt enable register ? comiid0: interrupt identification register ? comdiv2: 16-bit fractional baud divide register comtx, comrx, and comdiv0 share the same address location. comtx, comien0, and comrx can be accessed when bit 7 in the comcon0 register is cleared, and comdiv0 and comdiv1 can be accessed when bit 7 of comcon0 is set. uart tx register name: comtx address: 0xffff0700 access: write only function: writing to this 8-bit register transmits data using the uart. uart rx register name: comrx address: 0xffff0700 default value: 0x00 access: read only function: this 8-bit register is read from to receive data transmitted using the uart. uart divisor latch register 0 name: comdiv0 address: 0xffff0700 default value: 0x00 access: read/write function: this 8-bit register contains the least significant byte of the divisor latch that controls the baud rate at which the uart operates. uart divisor latch register 1 name: comdiv1 address: 0xffff0704 default value: 0x00 access: read/write function: this 8-bit register contains the most significant byte of the divisor latch that controls the baud rate at which the uart operates.
aduc7036 rev. b | page 105 of 132 uart control register 0 name: comcon0 address: 0xffff070c default value: 0x00 access: read/write function: this 8-bit register controls the operation of the uart in conjunction with comcon1. table 81. comcon0 mmr bit designations bit name description 7 dlab divisor latch access. set by user to enable access to comdiv0 and comdiv1. cleared by user to disable access to comdiv0 and comdiv1 and to enable access to comrx, comtx, and comien0. 6 brk set break. set by user to force txd to 0. cleared to operate in normal mode. 5 sp stick parity. set by user to force parity to defined values. 1 if eps = 1 and pen = 1. 0 if eps = 0 and pen = 1. 4 eps even parity select bit. set for even parity. cleared for odd parity. 3 pen parity enable bit. set by user to transmit and check the parity bit. cleared by user for no parity transmission or checking. 2 stop stop bit. set by user to transmit 1.5 stop bits if the word length is five bits, or two stop bits if the word length is six, seven, or eight bits. the receiver checks the first stop bit only, regardless of the number of stop bits selected. cleared by the user to generate one stop bit in the transmitted data. 1 to 0 wls word length select. 00 = five bits. 01 = six bits. 10 = seven bits. 11 = eight bits. uart control register 1 name: comcon1 address: 0xffff0710 default value: 0x00 access: read/write function: this 8-bit register controls the operation of the uart in conjunction with comcon0. table 82. comcon1 mmr bit designations bit name description 7 to 6 sms uart input mux. 00 = rxd driven by lin input; required for lin communications using the lin pin. 01 = reserved. 10 = rxd driven by gp5; required for serial comm unications using the gpio _5/irq1/rxd pin (rxd). 11 = reserved. 5 reserved. not used. 4 loopback loopback. set by user to enable loopback mode . in loopback mode, the txd is forced high. 3 to 0 reserved. not used.
aduc7036 rev. b | page 106 of 132 uart status register 0 name: comsta0 address: 0xffff0714 default value: 0x60 access: read only function: this 8-bit, read only register reflects the current status of the uart. table 83. comsta0 mmr bit designations bit name description 7 reserved. 6 temt comtx and shift register empty status bit. set automatically if comtx and the shift register are empty. this bit indicates that the data has been transmitted; that is, no more data is present in the shift register. cleared automatically by writing to comtx. 5 thre comtx empty status bit. set automatically if comtx is empty. comtx can be written as soon as the thre bit is set, but the previous data may not have been transmitted yet and may still be present in the shift register. cleared automatically by writing to comtx. 4 bi break indicator. set when sin is held low for more than the maximum word length. cleared automatically. 3 fe framing error. set when the stop bit is invalid. cleared automatically. 2 pe parity error. set when a parity error occurs. cleared automatically. 1 oe overrun error. set automatically if data is overwritten before being read. cleared automatically. 0 dr data ready. set automatically when comrx is full. cleared by reading comrx.
aduc7036 rev. b | page 107 of 132 uart interrupt enable register 0 name: comien0 address: 0xffff0704 default value: 0x00 access: read/write function: this 8-bit register enables and disables the individual uart interrupt sources. table 84. comien0 mmr bit designations bit name description 7 to 4 reserved. not used. 3 edssi reserved. this bit should be written as 0. 2 elsi rxd status interrupt enable bit. set by the user to enable genera tion of an interrupt if any of the comsta0[3:1] register bits are set. cleared by the user. 1 etbei enable transmit buffer empty interrupt. set by the user to enable an inte rrupt when the buffer is empty duri ng a transmission, that is, when comsta0[5] is set. cleared by the user. 0 erbfi enable receive buffer full interrupt. set by the user to enable an interrupt when the buffer is full during a reception. cleared by the user. uart interrupt identification register 0 name: comiid0 address: 0xffff0708 default value: 0x01 access: read only function: this 8-bit register reflects the source of the uart interrupt. table 85. comiid0 mmr bit designations bits[2:1] status bits bit 0 nint priority definition clearing operation 00 1 no interrupt 11 0 1 receive line status interrupt read comsta0 10 0 2 receive buffer full interrupt read comrx 01 0 3 transmit buffer empty interrupt write data to comtx or read comiid0 00 0 4 reserved reserved
aduc7036 rev. b | page 108 of 132 uart fractional divider register name: comdiv2 address: 0xffff072c default value: 0x0000 access: read/write function: this 16-bit register controls the operation of the fractional divider for the aduc7036. table 86. comdiv2 mmr bit designations bit name description 15 fben fractional baud rate generator enable bit. set by the user to enable the fractional baud rate generator. cleared by the user to generate the baud rate using the standard 450 uart baud rate generator. 14 to 13 reserved. 12 to 11 fbm[1:0] fractional divider m. if fbm = 0, m = 4. see equa tion 2 for the calculation of the baud rate using the m fractional divider and table 80 for common baud rate values. 10 to 0 fbn[10:0] fractional divider n. see equation 2 for the calcul ation of the baud rate using a fractional divider and table 80 for common baud rate values.
aduc7036 rev. b | page 109 of 132 serial peripheral interface the aduc7036 features a complete hardware serial peripheral interface (spi) on chip. spi is an industry-standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, that is, full duplex. in master mode, polarity and phase of the clock is controlled by the spicon register, and the bit rate is defined in the spidiv register using the spi baud rate calculation, as follows: the spi interface is operational only with core clock divider bits (powcon[2:0] = 0000 or 001). the spi port can be configured for master or slave operation and consists of four pins that are multiplexed with four gpios. the four spi pins are miso, mosi, sclk, and ss . the pins to which these signals are connected are shown in . table 87 table 87. spi output pins pin spi pin function description gp0 (gpio mode 1) ss chip select gp1 (gpio mode 1) sclk serial clock gp2 (gpio mode 1) miso master input, slave output gp3 (gpio mode 1) mosi master output, slave input miso pin the miso (master input, slave output) pin is configured as an input line in master mode and as an output line in slave mode. the miso line on the master (data in) should be connected to the miso line in the slave device (data out). the data is transferred as byte-wide (8-bit) serial data, msb first. mosi pin the mosi (master output, slave input) pin is configured as an output line in master mode and as an input line in slave mode. the mosi line on the master (data out) should be connected to the mosi line in the slave device (data in). the data is transferred as byte-wide (8-bit) serial data, msb first. sclk pin the sclk (master serial clock) pin is used to synchronize the data being transmitted and received through the mosi sclk period. therefore, a byte is transmitted/received after eight sclk periods. the sclk pin is configured as an output in master mode and as an input in slave mode. )1(2 mhz48.20 spidiv f clock serial + = (3) the maximum speed of the spi clock is dependent on the clock divider bits and is summarized in table 88 . table 88. spi speed vs. clock di vider bits in master mode setting of cd bits spidiv maximum sclk (mhz) 0 0x05 1.667 1 0x0b 0.833 in slave mode, the spicon register must be configured with the phase and polarity of the expected input clock. the slave accepts data of up to 5.12 mb from an external master when cd = 0. the formula to determine the maximum speed is as follows: 4 hclk clock serial f f = (4) in both master and slave modes, data is transmitted on one edge of the scl signal and sampled on the other. therefore, it is important to use the same polarity and phase configurations for the master and slave devices. ss pin in spi slave mode, a transfer is initiated by the assertion of ss , an active low input signal. the spi port transmits and receives eight bits of data, and then the transfer is concluded by the deassertion of ss . in slave mode, ss is always an input. spi register definitions t he following mmr registers are used to control the spi interface: ? spicon: 16-bit control register ? spista: 8-bit, read only status register ? spidiv: 8-bit, serial clock divider register ? spitx: 8-bit, write only transmit register ? spirx: 8-bit, read only receive register
aduc7036 rev. b | page 110 of 132 spi control register name: spicon address: 0xffff0a10 default value: 0x0000 access: read/write function: this 16-bit mmr configures the serial peripheral interface. table 89. spicon mmr bit designations bit description 15 to 13 reserved. 12 continuous transfer enable. set by the user to enable continuous transfer. in master mode , the transfer continues until no valid data is available in the spitx register. ss is asserted and remains asserted for the duration of each 8-bit serial transfer until spitx is empty. cleared by the user to disable continuous transfer. each transfer consists of a sing le 8-bit serial transfer. if valid data exists in the spitx register, a new transfer is initiated after a stall period. 11 loopback enable. set by the user to connect miso to mosi and test software. cleared by the user to be in normal mode. 10 slave output enable. set by the user to enable the slave output. cleared by the user to disable the slave output. 9 slave select input enable. set by the user in master mode to enable the output. cleared by the user to disable the output. 8 spirx overflow overwrite enable. set by the user; the valid data in the spirx regist er is overwritten by the new serial byte received. cleared by the user; the new serial byte received is discarded. 7 spitx underflow mode. set by the user to transmit the previous data. cleared by the user to transmit 0. 6 transfer and interrupt mode (master mode). set by the user to initiate a transfer with a write to th e spitx register. an interrupt occurs when spitx is empty. cleared by the user to initiate a transfer with a read of the spirx register. an interrupt occurs when spirx is full. 5 lsb first transfer enable bit. set by the user; the lsb is transmitted first. cleared by the user; the msb is transmitted first. 4 reserved. 3 serial clock polarity mode bit. set by the user; the se rial clock idles high. cleared by the user; the serial clock idles low. 2 serial clock phase mode bit. set by the user; the serial clock pulses at the beginning of each serial bit transfer. cleared by the user; the serial clock pulses at the end of each serial bit transfer. 1 master mode enable bit. set by the user to enable master mode. cleared by the user to enable slave mode. 0 spi enable bit. set by the user to enable the spi. cleared by the user to disable the spi.
aduc7036 rev. b | page 111 of 132 spi status register name: spista address: 0xffff0a00 default value: 0x00 access: read only function: this 8-bit mmr represents the current status of the serial peripheral interface. table 90. spista mmr bit designations bit description 7 to 6 reserved. 5 spirx data register overflow status bit. set if spirx is overflowing. cleared by reading the spirx register. 4 spirx data register irq. set automatically if bit 3 or bit 5 is set. cleared by reading the spirx register. 3 spirx data register full status bit. set automatically if valid data is present in the spirx register. cleared by reading the spirx register. 2 spitx data register underflow status bit. set automatically if spitx is underflowing. cleared by writing in the spitx register. 1 spitx data register irq. set automatically if bit 0 is cleared or bit 2 is set. cleared either by writing in the spitx register or, if the transmission is finished, by disabling the spi. 0 spitx data register empty status bit. set by writing to spitx to send data. this bit is set during transmission of data. cleared when spitx is empty. spi receive register name: spirx address: 0xffff0a04 default value: 0x00 access: read only function: this 8-bit mmr contains the data received using the serial peripheral interface. spi transmit register name: spitx address: 0xffff0a08 access: write only function: write to this 8-bit mmr to transmit data using the serial peripheral interface. spi divider register name: spidiv address: 0xffff0a0c default value: 0x1b access: read/write function: the 8-bit mmr represents the frequency at which the serial peripheral interface is operating. for more information on the calculation of the baud rate, refer to equation 3.
aduc7036 rev. b | page 112 of 132 serial test interface the aduc7036 incorporates single-pin, serial test interface (sti) ports that can be used for end-customer evaluation or diagnostics on finished production units. the sti port transmits from one byte to six bytes of data in 12-bit packets. as shown in figure 43 , each transmission packet includes a start bit, the transmitted byte (eight bits), an even parity bit, and two stop bits. the sti data is transmitted on the sti pin, and the baud rate is determined by the overflow rate of timer4. t he sti port is configured and controlled via six mmrs. ? stikey0: serial test interface key0 ? stikey1: serial test interface key1 ? stidat0: data0 (16-bit) holds two bytes ? stidat1: data1 (16-bit) holds two bytes ? stidat2: data2 (16-bit) holds two bytes ? sticon: controls the serial test interface serial test interface key0 register name: stikey0 address: 0xffff0880 access: write only function: the stikey0 mmr is used in conjunction with the stikey1 mmr to protect the sticon mmr. stikey0 must be written with 0x0007 immediately before any attempt to write to sticon. stikey1 must be written with 0x00b9 immedi- ately after sticon is written to ensure the sticon write sequence completes successfully. if stikey0 is not written, is written out of sequence, or is written incorrectly, any subsequent write to the sticon mmr is ignored. serial test interface key1 register name: stikey1 address: 0xffff0888 access: write only function: the stikey1 mmr is used in conjunction with the stikey0 mmr to protect the sticon mmr. stikey1 must be written with 0x00b9 immediately after any attempt to write to sticon. stikey0 must be written with 0x0007 immediately before sticon is written to ensure the sticon write sequence complets successfully. if stikey1 is not written, is written out of sequence, or is written incorrectly, any previous write to the sticon mmr is ignored. serial test interface data0 register name: stidat0 address: 0xffff088c default value: 0x0000 access: read/write function: the stidat0 mmr is a 16-bit register that holds the first and second data bytes that are to be transmitted on the sti pin as soon as the sti port is enabled. the first byte to be transmitted occupies bits[0:7], and the second byte occupies bits[8:15]. serial test interface data1 register name: stidat1 address: 0xffff0890 default value: 0x0000 access: read/write function: the stidat1 mmr is a 16-bit register that holds the third and fourth data bytes that are to be transmitted on the sti pin when the sti port is enabled. the third byte to be transmitted occupies bits[0:7], and the fourth byte occupies bits[8:15]. serial test interface data2 register name: stidat2 address: 0xffff0894 default value: 0x0000 access: read/write function: the stidat2 mmr is a 16-bit register that is used to hold the fifth and sixth data bytes that are to be transmitted on the sti pin when the sti port is enabled. the fifth byte to be transmitted occupies bits[0:7], and the sixth byte occupies bits[8:15]. parity bit start bit sti byte0 sti byte1 sti byte2 parity bit with two stop bits 07474-041 figure 43. serial adc test interface example, 3-byte transmission
aduc7036 rev. b | page 113 of 132 serial test interface control register name: sticon address: 0xffff0884 default value: 0x0000 a ccess: read/write access, write protected by two key registers (stikey0 and stikey1). a write access to sticon is completed correctly only if the following triple write sequence is followed: 1. stikey0 mmr is written with 0x0007. 2. sticon is written. 3. the sequence is completed by writing 0x00b9 to stikey1. function: the sti control mmr is an 16-bit register that configures the mode of operation of the serial test interface. note that the gpio_13 must be configured for sti operation in gp2con for sti communications. table 91. sticon mmr bit designations bit description 15 to 9 reserved. these bits are reserved for future use and should be written as 0 by user code. 8 to 5 state bits, read only. if the interface is in the middle of a transmission, these bits are not 0. 4 to 2 number of bytes to transmit. these bits select the numb er of bytes to be transmitted. user code must subsequently write the bytes to be transmitted into the stidat0, stidat1, and stidat2 mmrs. 000 = 1-byte transmission. 001 = 2-byte transmission. 010 = 3-byte transmission. 011 = 4-byte transmission. 100 = 5-byte transmission. 101 = 6-byte transmission. 1 reset serial test interface. 1 = resets the serial test interface. a subsequent read of sticon returns all 0s. 0 = operates in normal mode (default). 0 serial test interface enable. this bit is set by user code. 1 = enables the serial test interface. 0 = disables the serial test interface.
aduc7036 rev. b | page 114 of 132 serial test interface output structure the serial test interface is a high voltage output that incorporates a low-side driver, short-circuit protection, and diagnostic pin readback capability. the output driver circuit configuration is shown in figure 44 . sti pin readback hvmon[5] sti transmit gp2con[24] ref1 short-circuit protection control hvcfg1[2] sti 07474-042 figure 44. sti output structure using the serial test interface d ata begins transmission only when the sti port is configured as follows: ? configure timer4 for baud rate generation. ? correctly enable sticon using stikey0 and stikey1 for secure access. ? required bytes to be transmitted are written into stidat0, stidat1, and stidat2. timer4 is configured with the correct load value to generate an overflow at the required baud rate. if the sti port is being used to transmit adc conversion results, the baud rate must be suffi- cient to output each adc result (16-bits) before the next adc conversion result is available. for example, if the adc is sampling at 1 khz, the baud rate must be sufficient to output 36 bits as follows: (3 8 bits (16-bit adc result and a checksum byte, for example)) + (3 1 start bit) + (3 1 parity bit) + (3 2 stop bits) = 36 bits. therefore, the serial test interface must transmit data at greater than 36 kbps. the closest standard baud rate is 38.4 kbps; as such, the reload value written to the timer4 load mmr (t4ld) is 0x0106 (267 decimal). this value is based on a prescaler of 1 and is calculated as follows, using a core clock of 10.24 mhz: 267 kbps4.38 mhz24.10 = = = ratebaud desired frequency clockcore t4ld when the timer4 load value is written and the timer itself is configured and enabled using the t4con mmr, the sti port must be configured. this is accomplished by writing to the sticon mmr in a specific sequence using the stikey0 and stikey1 mmrs as described in the previous sections. finally, the sti port does not begin transmission until the required number of transmit bytes are written into the stidatx mmrs. as soon as sti starts transmitting, the value in the sticon mmr changes from the value initially written to this register. user code can ensure that all data is transmitted by continuously polling the sticon mmr until it reverts back to the value originally written to it. to disable the serial interface, user code must write a 0 to sticon[0]. example code an example code segment configuring the sti port to transmit five bytes and then to transmit two bytes follows: t4ld = 267; // timer4 reload value t4con = 0xc0; // enable t4, selecting core clock in periodic mode stikey0 = 07; // sticon start write sequence sticon = 0x11; // enable and transmit five bytes stikey1 = 0xb9; // sticon complete write stidat0 = 0xaabb; // five bytes for stidat1 = 0xccdd; // transmission stidat2 = 0xff; while(sticon = 0x09) // wait for transmission to complete stikey0 = 07; // sticon start write sequence sticon = 0x05; // enable and transmit two bytes stikey1 = 0xb9; // sticon complete write stidat0 = 0xeeff; // two bytes for transmission while(sticon = 0x09) // wait for transmission to complete
aduc7036 rev. b | page 115 of 132 lin (local interconnect network) interface the aduc7036 features high voltage physical interfaces between the arm7 mcu core and an external lin bus. the lin inter- face operates as a slave only interface, operating from 1 kbaud to 20 kbaud, and it is compatible with the lin 2.0 standard. the pull-up resistor required for a slave node is on chip, reducing the need for external circuitry. the lin protocol is emulated using the on-chip uart, an irq, a dedicated lin timer, and the high voltage transceiver (also incorporated on chip) as shown in figure 45 . the lin is clocked from the low power oscillator for the break timer, and a 5 mhz output from the pll is used for the synchronous byte timing. lin mmr description th e lin hardware synchronization (lhs) functionality is con- trolled through five mmrs. the function of each mmr is as follows: ? l hssta: lhs status register. this mmr contains infor- mation flags that describe the current status on the interface. ? l hscon0: lhs control register 0. this mmr controls the configuration of the lhs timer. ? lhscon1: lhs start and stop edge control register. this mmr dictates on which edge of the lin synchronization byte the lhs starts/stops counting. ? lhsval0: lhs synchronization 16-bit timer. this mmr is controlled by lhscon0. ? lhsval1: lhs break timer register. gpio_12 function select gp2con[20] gpio_12 gp2dat[29] and gpsdat[21] uart lhs hardware rxd txd bpf internal short-circuit trip reference internal short-circuit sense resistor short-circuit control hvcfg1[2] output disable lin mode hvcfg0[1:0] input voltage threshold reference lin enable (internal pull-up) hvcfg0[5] four lin interrupt sources: break lhssta[0] start lhssta[1] stop lhssta[2] break error lhssta[4] vdd rxd enable lhscon0[8] lhsval0 lhsval1 lhs interrupt irqen[7] 5mhz 131khz lhs interrupt logic vdd scr io_vss overvoltage protection external lin pin master ecu protection diode master ecu pull-up c load 0 7474-043 figure 45. lin i/o block diagram
aduc7036 rev. b | page 116 of 132 lin hardware synchronization status register name: lhssta address: 0xffff0780 default value: 0x00000000 access: read only function: this lhs status register is a 32-bit register whose bits reflect the current operating status of the lin interface. table 92. lhssta mmr bit designations bit description 31 to 7 reserved. these read only bits are reserved for future use. 6 rising edge detected (bsd mode only). set to 1 by hardware to indicate a rising edge has been detected on the bsd bus. cleared to 0 after user code reads the lhssta mmr. 5 lhs reset complete flag. set to 1 by hardware to indicate an lhs reset command has completed successfully. cleared to 0 after user code reads the lhssta mmr. 4 break field error. set to 1 by hardware and generates an lhs interrupt (i rqen[7]) when the 12-bit break timer (lhsval1) register overflows to indicate the lin bus has stayed low too long, thus indicating a possible lin bus error. cleared to 0 after user code reads the lhssta mmr. 3 lhs compare interrupt. set to 1 by hardware when the value in lhsval0 (lin sync hronization bit timer) equals the value in the lhscmp register. cleared to 0 after user code reads the lhssta mmr. 2 stop condition interrupt. set to 1 by hardware when a stop condition is detected. cleared to 0 after user code reads lhssta mmr. 1 start condition interrupt. set to 1 by hardware when a start condition is detected. cleared to 0 after user code reads lhssta mmr. 0 break timer compare interrupt. set to 1 by hardware when a valid lin break condition is detected. a lin break condition is generated when the lin break timer value reaches the break timer compare value (see the lhsval1 in the lin hardware synchronization break timer1 register section for more information). cleared to 0 after user code reads the lhssta mmr.
aduc7036 rev. b | page 117 of 132 lin hardware synchronization control register 0 name: lhscon0 address: 0xffff0784 default value: 0x00000000 access: read/write function: this 16-bit lhs control register, in conjunction with the lhscon1 register, is used to configure the lin mode of oper ation. table 93. lhscon0 mmr bit designations bit description 15 to 13 reserved. these bits are reserved for future use and should be written as 0 by user software. 12 rising edge detected interrupt disable. mode description bsd mode set to 1 to disable the rising edge detected interrupt. cleared to 0 to enable the break rising edge detected interrupt. lin mode set to 1 to enable the rising edge detected interrupt. cleared to 0 to disable the break rising edge detected interrupt. 11 break timer compare interrupt disable. set to 1 to disable the break timer compare interrupt. cleared to 0 to enable the break timer compare interrupt. 10 break timer error interrupt disable. set to 1 to disable the break timer error interrupt. cleared to 0 to enable the break timer error interrupt. 9 lin transceiver, standalone test mode. set to 1 by user code to enable the external gpio_7 and gpio _8 pins to drive the lin transceiver txd and the lin transceiver rxd, respectively, independent of the uart. the functions of gpio _7 and gpio_8 should first be configured by user code via the gpio_7 function select bit 0 and gpio_8 fu nction select bit 4 in the gp2con register. cleared to 0 by user code to operate the lin in norm al mode, it is driven directly from the on-chip uart. 8 gate uart/bsd r/ w bit. mode description uart mode set to 1 by user code to disable the internal uart rx d (receive data) by gating it high until both the break field and subsequent lin sync byte are detected. this ensures that during break or sync field periods the uart does not receive any spurious se rial data that has to be flushed out of the uart before valid data fields can be received. cleared to 0 by user code to enable the internal uart rxd (receive data) after the break field and subsequent lin sync byte have been detected so that the uart can receive the subsequent lin data fields. bsd read mode 1 set to 1 by user code to enable the generation of a br eak condition interrupt (lhssta[0]) on a rising edge of the bsd bus. the break timer (lhsval1) starts counting on the falling edge and stops counting on the rising edge, where an interrupt is generated, allowing user code to determine if a 0, 1, or sync pulse width has been received. note that the break timer generates an interrupt if the value in the lin break timer (lhsval1 read value) equals the break timer compare value (lhsv al1 write value), and if the break timer overflows. this configuration can be used in bsd read mode to detect fault conditions on the bsd bus. bsd write mode 1 cleared to 0 by user code to disable the generation of break condition interrupts on a rising edge of the bsd bus. the lhs compare interrupt bit (lhssta[3]) is used to determine when the mcu should release the bsd bus while transmitting data. if the break condition in terrupt is still enabled, it generates an unwanted interrupt as soon as the bsd bus is deasserted. as in bsd read mode, the break timer stops counting on a rising edge; therefore, the break timer can also be used in this mode to allow user code to confirm the pulse width in transmitted data bits. 7 sync timer stop edge type bit. set to 1 by user code to stop the sync timer on the risi ng edge count configured through the lhscon1[7:4] register. cleared to 0 by user code to stop the sync timer on the falling edge count configured through the lhscon1[7:4] register. 6 mode of operation bit. set to 1 by user code to select bsd mode of operation. cleared to 0 by user code to select lin mode of operation.
aduc7036 rev. b | page 118 of 132 bit description 5 enable compare interrupt bit. set to 1 by user code to generate an lhs interrupt (irqen[7]) when the value in lhs val0 (the lin synchronization bit timer) equals the value in the lhscmp register. the lhs compare interrup t bit, lhssta[3], is set when this interrupt occurs. this configuration is used in bsd write mode to allow user code to correctly time the outp ut pulse widths of bsd bits to be transmit ted. cleared to 0 by user code to disable compare interrupts. 4 enable stop interrupt. set to 1 by user code to generate an interrupt when a stop condition occurs. cleared to 0 by user code to disable interrupts when a stop condition occurs. 3 enable start interrupt. set to 1 by user code to generate an interrupt when a start condition occurs. cleared to 0 by user code to disable interrupts when a start condition occurs. 2 lin sync enable bit. set to 1 by user code to enable lhs functionality. cleared to 0 by user code to disable lhs functionality. 1 edge counter clear bit. set to 1 by user code to clear the inte rnal edge counters in the lhs peripheral. cleared automatically to 0 after a 15 s delay. 0 lhs reset bit. set to 1 by user code to reset all lhs logic to default conditions. cleared automatically to 0 after a 15 s delay. 1 in bsd mode, lhscon0[6] is set to 1. because of the finite propagation delay in the bsd transmit (from the mcu to the external pin) and receive (from the external pin to the mcu) paths, user code must not switch between bsd write and read modes until the mcu confirms that the external bsd pin is deasserted. fail ure to adhere to this recommendation may result in the genera tion of an inadvertent break condition interrupt after user code switches from bsd write mode to bsd read mode. a stop condition interrupt can be used to ensure that this scenario is avoided. lin hardware synchronization control register 1 name: lhscon1 address: 0xffff078c default value: 0x00000032 access: read/write function: this 32-bit lhs control register, in conjunction with the lhscon0 register, is used to configure the lin mode of oper ation. table 94. lhscon1 mmr bit designations bit description 31 to 8 reserved. these bits are reserved for future use and should be written as 0 by user software. 7 to 4 lin stop edge count. set by user code to the number of fa lling or rising edges on which to stop the internal lin synchronization counter. the stop value of this counter can be read by user code using lhsval0. the type of edge, either rising or falling, is configured by lhscon0[7]. the default va lue of these bits is 0x3, which configures the hardware to stop counting on the third falling edge. note that the first falling edge is considered to be the falling edge at the start of the lin break pulse. 3 to 0 lin start edge count. these four bits are set by user code to the number of falling edges that must occur before the internal lin synchronization timer starts counting. the stop value of this counter can be read by user code using lhsval0. the default value of these bits is 0x2, which configures the hardware to start counting on the second falling edge. note that the first falling edge is considered to be the falling edge at the start of the lin break pulse.
aduc7036 rev. b | page 119 of 132 lin hardware synchronization timer0 register name: lhsval0 address: 0xffff0788 default value: 0x0000 access: read only function: this 16-bit, read only register holds the value of the internal lin synchronization timer. the lin synchronization timer is clocked from an internal 5 mhz clock and is indepen- dent of core clock and baud rate frequency. in lin mode, the value read by user code from the lhsval0 register can be used to calculate the master lin baud rate. this calculation is then used to configure the internal uart baud rate to ensure correct lin communication via the uart from the aduc7036 slave to the lin master node. lin hardware synchronizatio n break timer1 register name: lhsval1 address: 0xffff0790 default value: 0x0000 access: read/write function: when user code reads this location, the 12-bit value returned is the value of the internal lin break timer, which is clocked directly from the on-chip low power 131 khz oscillator and times the lin break pulse. a negative edge on the lin bus or user code reading the lhsval1 results in the timer and the register contents being reset to 0. when user code writes to this location, the 12-bit value is written not to the lin break timer but to a lin break compare register. in lin mode of operation, the value in the compare register is continuously compared to the break timer value. a lin break interrupt (irqen[7] and lhssta[0]) is generated when the timer value reaches the compare value. after the break condition interrupt, the lin break timer continues to count until the rising edge of the break signal. if a rising edge is not detected and the 12-bit timer overflows (4096 1/131 khz = 31 ms), a break field error interrupt (irqen[7] and lhssta[4]) is generated. by default, the value in the compare register is 0x0047, corresponding to 11 bit periods (that is, the minimum pulse width for a lin break pulse at 20 kbps). for different baud rates, this value can be changed by writing to lhsval1. note that if a valid break interrupt is not received, subsequent sync pulse timing through the lhsval0 register does not occur. lin hardware interface lin frame protocol the lin frame protocol is broken into four main categories: break symbol, sync byte, protected identifier, and data bytes. the format of the frame header, break symbol, synchronization byte, and protected identifier is shown in figure 46 . essentially, the embedded uart, the lin hardware synchronization logic, and the high voltage transceiver interface all combine on chip to support and manage lin-based transmissions and receptions. lin frame break symbol as shown in figure 47 , the lin break symbol, which lasts at least 13 bit periods, is used to signal the start of a new frame. the slave must be able to detect a break symbol even while expecting or receiving data. the aduc7036 accomplishes this by using the lhsval1 break condition and break error detect functionality as described in the lin hardware synchronization break timer1 register section. the break period does not have to be accurately measured, but if a bus fault condition (bus held low) occurs, it must be flagged. lin frame synchronization byte the baud rate of the communication using lin is calculated from the sync byte, as shown in figure 48 . the time between the first falling edge of the sync field and the fifth falling edge of the sync field is measured and then divided by 8 to determine the baud rate of the data that is to be transmitted. the aduc7036 implements the timing of this sync byte in hardware. for more information about this feature, see the lin hardware synchronization status register section. lin frame protected identifier after receiving the lin sync field, the required baud rate for the uart is calculated. the uart is then configured, allowing the aduc7036 to receive the protected identifier, as shown in figure 49 . the protected identifier consists of two subfields: the identifier and the identifier parity. the 6-bit identifier contains the identifier of the target for the frame. the identifier signifies the number of data bytes to be either received or transmitted. the number of bytes is user configurable at the system-level design. the parity is calculated on the identifier and is dependent on the revision of lin for which the system is designed. lin frame data byte the data byte frame carries between one and eight bytes of data. the number of bytes contained in the frame is dependent on the lin master. the data byte frame is split into data bytes, as shown in figure 50 .
aduc7036 rev. b | page 120 of 132 lin frame data transmission and reception t o manage data on the lin bus requires use of the following uart mmrs: w hen the break symbol and synchronization byte have been correctly received, data is transmitted and received via the comtx and comrx mmrs, after uart is configured to the required baud rate. to configure the uart for use with lin requires the use of the following uart mmrs: ? comtx: 8-bit transmit register ? comrx: 8-bit receive register ? comcon0: line control register ? comsta0: line status register ? comdiv0: divisor latch (low byte). in addition, transmitting data on the lin bus requires that the relevant data be placed into comtx, and reading data received on the lin bus requires the monitoring of comrx. to ensure that data is received or transmitted correctly, comsta0 should be monitored. for more information, see the uart serial interface and uart register definitions sections. ? comdiv1: divisor latch (high byte). ? comdiv2: 16-bit fractional baud divide register. the required values for comdiv0, comdiv1, and comdiv2 are derived from the lhsval0, to generate the required baud rate. ? comcon0: line control register. as soon as the uart is correctly configured, the lin protocol for receiving and transmitting data is identical to the uart specification. under software control, it is possible to multiplex the uart data lines (txd and rxd) to the external gpio_7/irq4 and gpio_8/irq5 pins. for more information, see the gpio port1 control register (gp1con) section. 13 t bit 2 t bit 2 t bit 2 t bit 2 t bit >1 t bit > = 14 t bit 8 t bit break sync sta s0 s1 s2 s3 s4 s5 s6 s7 sto protected id 07474-044 t break > 13 t bit figure 46. lin interface timing break delimit start bit 07474-045 figure 47. lin break field t bit st bi start bit op t 07474-046 figure 48. lin sync byte field id1 id0 start bit st bi t bit op t id2 id3 id4 id5 p0 p1 07474-047 figure 49. lin identifier byte field bit1 bit0 start bit st bi op t t bit bit2 bit3 bit4 bit5 bit6 bit7 07474-048 figure 50. lin data byte field
aduc7036 rev. b | page 121 of 132 example lin hardware synchronization routine using the following c-source code lin initialization routine, lhsval1 begins to count on the first falling edge received on the lin bus. if lhsval1 exceeds the value written to lhsval1, in this case 0x3f, a break compare interrupt is generated. on the next falling edge, lhsval0 begins counting. lhsval0 monitors the number of falling edges and compares it to the value written to lhscon1[7:4]. in this example, the number of edges to monitor is six falling edges of the lin frame, or the five falling edges of the sync byte. when this number of falling edges is received, a stop condition interrupt is generated. it is at this point that the uart is configured to receive the protected identifier. the uart must be gated through lhscon0[8] before the lin bus returns high. if the lin bus returns high when uart is not gated, uart communication errors may occur. this process is shown in detail in figure 51 . example code to ensure the success of this process follows figure 49. void lin_init(void ) { char hvstatus; gp2con = 0x110000; // enable lhs on gpio pins lhscon0 = 0x1; // reset lhs interface do{ hvdat = 0x02; // enable normal lin tx mode hvcon = 0x08; // write to config0 do{ hvstatus = hvcon; } while(hvstatus & 0x1); // wait until command is finished } while (!(hvstatus & 0x4)); // transmit command is correct while((lhssta & 0x20) == 0 ) { // wait until the lhs hardware is reset } lhscon1 = 0x062; // sets stop edge as the fifth falling edge // and the start edge as the first falling // edge in the sync byte lhscon0 = 0x0114; // gates uart rx line, ensuring no interference // from the lin into the uart // selects the stop condition as a falling edge // enables generation of an interrupt on the // stop condition // enables the interface lhsval1 = 0x03f; // sets number of 131 khz periods to generate a break interrupt // 0x3f / 131 khz ~ 480 s, which is just over 9.5 tbits id1 id0 start bit start bit stop bit stop bit id2 id3 id4 id5 p0 p1 t bit lhsval1 = 0x3f lhsval1 resets and starts counting break compare interrupt is generated lhsval0 starts counting lhsval0 stops counting and a stop interrupt is generated uart is configured, lhs interrupts disabled except break compare begins receiving data via uart 07474-049 figure 51. example lin configuration while((gp2dat & 0x10 ) == 0 ) {} // wait until lin bus returns high lhscon0 = 0x4; // enable lhs to detect break condition ungate rx line // disable all interrupts except break compare interrupt irqen = 0x800; // enable uart interrupt // the uart is now configured and ready to be used for lin
aduc7036 rev. b | page 122 of 132 lin diagnostics the aduc7036 features the capability to nonintrusively monitor the current state of the lin/bsd pin. this readback functionality is implemented using gpio_11. the current state of the lin/bsd pin is contained in gp2dat[4]. it is also possible to drive the lin/bsd pin high and low through user software, allowing the user to detect open-circuit conditions. this functionality is implemented via gpio_12. to enable this functionality, gpio_12 must be configured as a gpio through gp2con[20]. after it is configured, the lin/bsd pin can be pulled high or low using gp2dat. the aduc7036 also features short-circuit protection on the lin/bsd pin. if a short-circuit condition is detected on the lin/bsd pin, hvsta[2] is set. this bit is cleared by reenabling the lin driver using hvcfg1[3]. it is possible to disable this feature through hvcfg1[2]. lin operation during thermal shutdown when a thermal event occurs, that is, when hvsta[3] is set, lin communications continue uninterrupted.
aduc7036 rev. b | page 123 of 132 bit serial device (bsd) interface bsd is a pulse-width-modulated signal with three possible states: sync, 0, and 1. these are detailed, along with their associated tolerances, in table 95 . the frame length is 19 bits, and commu- nication occurs at 1200 bps 3%. table 95. bsd bit level description parameter min typ max unit txd rate 1164 1200 1236 bps b i t e n c o d i n g t sync 1/16 2/16 3/16 t period t 0 5/16 6/16 8/16 t period t 1 10/16 12/16 14/16 t period bsd communication hardware interface the aduc7036 emulates the bsd communication protocol using a gpio, an irq, and the lin synchronization hardware, all of which are under software control. gpio_12 function select gp2con[20] gpio_12 gp2dat[29] and gpsdat[21] rxd txd bpf internal short-circuit trip reference internal short-circuit sense resistor short-circuit control hvcfg1[2] output disable lin mode hvcfg0[1:0] input voltage threshold reference pull-up) hvcfg0[5] rxd enable lhscon0[8] lin enable (internal four lin interrupt sources break lhssta[0] start lhssta[1] stop lhssta[2] break error lhssta[4] vdd lhsval0 lhsval1 lhs interrupt irqen[7] 5mhz 131khz lhs interrupt logic vdd scr io_vss overvoltage protection external lin pin master ecu protection diode master ecu pull-up c load aduc7036 uart aduc7036 lhs hardware 0 7474-050 figure 52. bsd i/o hardware interface
aduc7036 rev. b | page 124 of 132 bsd related mmrs t he aduc7036 emulates the bsd communication protocol using a software (bit bang) interface with some hardware assis- tance form lin hardware synchronization logic. in effect, the aduc7036 bsd interface uses the following protocols: ? an internal gpio signal (gpio_12) that is routed to the external lin/bsd pin and is controlled directly by software to generate 0s and 1s. ? when reading bits, the lin synchronization hardware uses lhsval1 to count the width of the incoming pulses so that user code can interpret the bits as sync, 0, or 1. ? when writing bits, user code toggles a gpio pin and uses the lhscap and lhscmp registers to time pulse widths and generate an interrupt when the bsd output pulse width has reached its required width. t he aduc7036 mmrs required for bsd communication are as follows: ? lhssta: lin hardware synchronization status register ? lhscon0: lin hardware synchronization control register ? lhsval0: lin hardware synchronization timer0 (16-bit timer) ? lhscon1: lin hardware synchronization edge setup register ? lhsval1: lin hardware synchronization break timer ? lhscap: lin hardware synchronization capture register ? lhscmp: lin hardware synchronization compare register ? irqen/irqclr: enable interrupt register ? fiqen/fiqclr: enable fast interrupt register ? gp2dat: gpio port 2 data register ? gp2set: gpio port 2 set register ? gp2clr: gpio port 2 clear register detailed bit definitions for most of these mmrs have been listed previously. in addition to the registers described in the lin mmr description section, lhscap and lhscmp are registers that are required for the operation of the bsd interface. details of these registers follow. lin hardware synchronization capture register name: lhscap address: 0xffff0794 default value: 0x0000 access: read only function: this 16-bit, read only register holds the last captured value of the internal lin synchronization timer (lhsval0). in bsd mode, lhsval0 is clocked directly from an internal 5 mhz clock, and its value is loaded into the capture register on every falling edge of the bsd bus. lin hardware synchronization compare register name: lhscmp address: 0xffff0798 default value: 0x0000 access: read/write function: this register is used to time bsd output pulse widths. when enabled through lhscon0[5], a lin interrupt is generated when the value in lhscap equals the value written in lhscmp. this functionality allows user code to determine how long a bsd transmission bit (sync, 0, or 1) should be asserted on the bus.
aduc7036 rev. b | page 125 of 132 bsd communication frame to transfer data between a master and slave, or vice versa, the construction of a bsd frame is required. a bsd frame contains seven key components: pause/sync, a direction (dir) bit, the slave address, the register address, data, parity bits (p1 and p2), and the acknowledge bit from the slave. if the master is transmitting data, all bits except the acknowledge bit are transmitted by the master. i f the master is requesting data from the slave, the master transmits the pause/sync, direction bit, slave address, register address, and p1. the slave then transmits the data bytes, the p2 bit, and the acknowledge bit in the following sequence: 1. pause: three synchronization pulses 2. dir: signifies the direction of data transfer dir = 0 if master sends request d ir = 1 if slave sends request 3. slave address 4. register address: defines register to be read or written 5. bit 3 is set to write and cleared to read 6. data: 8-bit read only receive register 7. p1 and p2 p1 = 0 if even number of 1s in eight previous bits p1 = 1 if odd number of 1s in eight previous bits p2 = 0 if even number of 1s in data-word p2 = 1 if odd number of 1s in data-word 8. acknowledge bit ack = 0 if transmission is successful the acknowledge bit is always transmitted by the slave to indicate whether the information was received or transmitted. table 96. bsd protocol description pause dir slave address register address p1 data p2 ack 3 bits 1 bit 3 bits 4 bits 1 bit 8 bits 1 bit 1 bit bsd example pulse widths an example of the different pulse widths is shown in figure 53 . for each bit, the period for which the bus is held low defines what type of bit it is. if the bit is a sync bit, the pulse is held low for one bit. if the bit is 0, the pulse is held low for three bits. if the bit is 1, the pulse is held low for six bits. if the master is transmitting data, the signal is held low for the duration of the signal by the master. an example of a master transmitting a 0 is shown in figure 54 . if the slave is transmitting data, the master pulls the bus low to begin communication. the slave must pull the bus low before t sync elapses and then hold the bus low until either t 0 or t 1 has elapsed, after which time the bus is released by the slave. an example of a slave transmitting a 0 is shown in figure 55 . t sync t 0 07474-051 t 1 figure 53. bsd bit transmission bus pulled low by master t sync bus released by master after t 0 07474-052 t 0 figure 54. bsd master transmitting a 0 bus pulled low by master bus released by slave after t 0 bus held low by slave released by master t sync 07474-053 t 0 figure 55. bsd slave transmitting a 0 typical bsd program flow because bsd is a pwm communication protocol controlled by software, the user must construct the required data from each bit. for example, in constructing the slave address, the slave node receives the three bits and the user constructs the relevant address. when bsd communication is initiated by the master, data is transmitted and received by the slave node. a flowchart showing this process is shown in figure 56 .
aduc7036 rev. b | page 126 of 132 transmit to mast data er transmit se parity cond bit receive data from master receive second parity bit receive synchronization pulses receive direction bit receive slave address receive register address receive first parity bit bsd data transmission transmit ack/nack initialize bsd hardware/ software user code forces the gpio_12 signal low for a specified time to transmit data in bsd mode. in addition, user code uses the sync timer (lhsval0), the lhs sync capture register (lhscap), and the lhs sync compare register (lhscmp) to determine the length of time that the bsd bus should be held low for bit transmissions in the 0 or 1 state. as described in the bsd example pulse widths section, even when the slave is transmitting, the master always starts the bit transmission period by pulling the bsd bus low. if bsd mode is selected (lhscon0[6] = 1), the lin sync timer value is captured in lhscap on every falling edge of the bsd bus. the lin sync timer runs continuously in bsd mode. then, user code can immediately force gpio_12 low and read the captured timer value from lhscap. next, the user can calcu- late how many clock periods (with a 5 mhz clock) should elapse before the gpio_12 is driven high for a pulse width in the 0 or 1 state. the calcaulated number can be added to the lhscap value and written into the lhscmp register. if lhscon0[5] is set, the sync timer, which continues to count (being clocked by a 5 mhz clock), eventually equals the lhscmp value and generates an lhs compare interrupt (lhssta[3]). the response to this interrupt should be to force the gpio_12 signal (and, therefore, the bsd bus) high. the software control of the gpio_12 signal, along with the correct use of the lin synchronization timers, ensures that valid pulse widths in the 0 and 1 states can be transmitted from the aduc7036, as shown in figure 58 . again, care must be taken if switching from bsd write mode to bsd read mode, as described in table 93 (see the lhscon0[8] bit.) 07474-054 figure 56. bsd slave node state machine lhsval0 loaded into lhscap here bsd data reception to receive data, the lin/bsd peripheral must first be con- figured in bsd mode where lhscon0[6] = 1. in this mode, lhscon0[8] should be set to ensure that the lhs break timer (see the lin hardware synchronization break timer1 register section) generates an interrupt on the rising edge of the bsd bus. the lhs break timer is cleared and starts counting on the falling edge of the bsd bus; the timer is subsequently stopped and generates an interrupt on the rising edge of the bsd bus. given that the lhs break timer is clocked by the low power 131 khz oscillator, the value in lhsval1 can be interpreted by user code to determine if the received data bit is a bsd sync pulse, 0, or 1. bsd period in 0 state bsd period in 1 state lhsval1 cleared and starts counting on this edge 1 lhsval1 stopped and generates interrupt on this edge 2 07474-055 figure 57. master transmit, slave read bsd period in 0 state bsd period in 1 state 2 master drives bsd bus low 1 software asserts bsd low here 3 software deasserts bsd high here 5 lhscmp = lhsval0 interrupt generated here 4 07474-056 figure 58. master read, slave transmit wake-up from bsd interface the mcu core can be awakened from power-down via the bsd physical interface. before entering power-down mode, user code should enable the start condition interrupt (lhscon0[3]). when this interrupt is enabled, a high-to-low transition on the lin/bsd pin generates an interrupt event and wakes up the mcu core.
aduc7036 rev. b | page 127 of 132 part identification two registers mapped into the mmr space are intended to allow user code to identify and trace manufacturing lot id information, part id number, silicon mask revision, and kernel revision. this information is contained in the sysser0 and sysser1 mmr (see table 98 and table 99 for more information). in addition, the fee0adr mmr contains information at power-up that can identify the aduc7036 family member. for direct traceability, the assembly lot id, which can be 64 bits long, is also available. the sysali mmr contains the 32-bit lower half of the assembly lot id, and the upper half is contained in the t1ld mmr at power-up. the information contained in sysser0, sysser1, sysali, and t1ld allows full traceability of each part. the lot number is part of the branding on the package as shown in table 97 . table 97. branding example line lfcsp line 1 aduc7036 line 2 bcpz line 3 a40 # date code line 4 assembly lot number system serial id register 0 name: sysser0 address: 0xffff0238 default value: 0x00000000 (updated by kernel at power-on) access: read/write function: at power-on, this 32-bit register holds the value of the original manufacturing lot number from which this specific a duc7036 unit was manufactured (bottom die only). used in conjunction with sysser1, this lot number allows the full manufacturing histor y of this part to be traced (bottom die only). table 98. sysser0 mmr bit designations bit description 31 to 27 wafer number. the five bits read from this location give the wa fer number (1 to 24) from the wafer fabrication lot id (from whi ch this device originated). when used in conjunction with sysser0[26:0], it provides individual wafer traceability. 26 to 22 wafer lot fabrication plant. the five bits read from this location reflect the manufa cturing plant associated with this wafer l ot. when this information is used in conjunction with sysser0[21:0], it provides wafer lot traceability. 21 to 16 wafer lot fabrication id. the six bits read from this location form part of the wafe r lot fabrication id and, when used in conjunction with sysser0[26:22] and sysser0[15:0], provide wafer lot traceability. 15 to 0 wafer lot fabrication id. these 16 lsbs hold a 16-bit number to be interpreted as the wafer fabrication lot id number. when used in conjunction with the value in sysser1, that is, the manu facturing lot id, this number is a unique identifier for the pa rt.
aduc7036 rev. b | page 128 of 132 system serial id register 1 name: sysser1 address: 0xffff023c default value: 0x00000000 (updated by kernel at power-on) access: read/write function: at power-on, this 32-bit register holds the values of the part id number, silicon mask revision number, and kernel re vision number (bottom die only), as detailed in tabl e 99 . table 99. sysser1 mmr bit designations bit description 31 to 28 silicon mask revision id. the four bits read from this nibble reflect the silicon mask id number. specifically, the hexadecimal value in this nibble should be decoded as the lower nibble, refl ecting the ascii characters in the range of a to o. for example , if bits[19:16] = 0001 = 0x1, this value should be interpreted as 41, which is ascii character a corresponding to silicon mask revision a. if bits[19:16] = 1011 = 0xb, the number is interprete d as 4b, which is ascii character k, corresponding to silicon mask revision k. the allowable range for this value is 1 to 15, which is interpreted as 41 to 4f or ascii character a to character o. 27 to 20 kernel revision id. this byte contains the hexadecimal number, which should be interpreted as an ascii character indicating the revision of the kernel firmware embedded in the on-chi p flash/ee memory. for example, reading 0x41 from this byte should be interpreted as a, indicati ng a revision a kernel is on chip. 19 to 16 reserved. for prerelease samples, these bits refer to the kernel minor revision number of the device. 15 to 0 part id. these 16 lsbs hold a 16-bit number that is interprete d as the part id number. when used in conjunction with the value in sysser0 (that is, the manufacturing lot id), this number is a unique identifier for the part. system assembly lot id name: sysali address: 0xffff0560 default value: 0x00000000 (updated by kernel at power-on) access: read/write function: at power-on, this 32-bit register holds the lower half of the assembly lot id. for example, the assembly lot id is 01308640, sysali contains 0x38363430, and t1ld contains 0x30313330 at power-on. system kernel checksum name: syschk address: 0xffff0240 default value: 0x00000000 (updated by kernel at power-on) access: read/write function: at power-on, this 32-bit register holds the kernel checksum.
aduc7036 rev. b | page 129 of 132 system identification fee0adr name: fee0adr address: 0xffff0e10 default value: nonzero access: read/write function: this 16-bit register dictates the address upon which any flash/ee command executed via fee0con acts. note that this mmr is also used to identify the aduc7036 family member and prerelease silicon revision. table 100. fee0adr system identi fication mmr bit designations bit description 15 to 4 reserved 3 to 0 aduc703x family id 0x2 = aduc7032 0x3 = aduc7033 0x4 = aduc7034 0x6 = aduc7036 others = reserved for future use
aduc7036 rev. b | page 130 of 132 schematic this example schematic represents a basic functional circuit implem entation. additional components need to be added to ensure t hat the system meets any emc and other overvoltage/overcurrent compliance requirements. 13 42 19 20 24 33 48 1 18 15 22 21 8 10 34 35 47 44 gnd_sw agnd agnd dgnd dgnd dgnd io_vss vss vtemp ntc reg_avdd reg_dvdd lin/bsd tdo 12 tms 6 tck jtag adaptor 11 ntrst 7 tdi reset reg_dvdd 0.1f 220p 10f 10nf 0.47f 33h iin? iin+ in+ battery ground terminal reg_avdd shunt vbat vdd 10? 27.4 ? vbat f 2.2f lin master aduc7036 07474-057 figure 59. simplified schematic
aduc7036 rev. b | page 131 of 132 outline dimensions pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 5.2 5. 4.9 5 10 sq 5 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pi in n 1 dicator coplanarity 0.08 seating plane 0.25 min exposed pad (bottom view) for proper conne the exposed pad, r the pin configurat function descripti section of this dat compliant to jedec standards mo-220-vkkd-2 080108-a ction of efer to ion and ons a sheet. figure 60. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-1) dimensions shown in millimeters ordering guide model 1 temperature range package description model information package option aduc7036bcpz ?40c to +115c 48-lead lead frame ch ip scale package [lfcsp_vq] 10 mhz cp-48-1 aduc7036bcpz-rl ?40c to +115c 48-lead lead frame chip scale package [lfcsp_vq] 10 mhz cp-48-1 aduc7036ccpz ?40c to +115c 48-lead lead frame ch ip scale package [lfcsp_vq] 20 mhz cp-48-1 ADUC7036CCPZ-RL ?40c to +115c 48-lead lead frame chip scale package [lfcsp_vq] 20 mhz cp-48-1 eval-aduc7036qspz evaluation board 10 mhz 1 z = rohs compliant part.
aduc7036 rev. b | page 132 of 132 notes ?2008C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07474-0-5 /10(b)

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